參數(shù)資料
型號: SAA6712E
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)學(xué)處理器
英文描述: ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
中文描述: GRAPHICS PROCESSOR, PBGA292
封裝: 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁數(shù): 58/64頁
文件大?。?/td> 228K
代理商: SAA6712E
1999 Aug 25
58
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
Fig.18 Data timing diagram.
t
su(i)
: input set-up time; data input must be stable before active clock edge.
t
h(i)
: input hold time; data input must be stable after active clock edge.
t
PD(o)
: output propagation delay; output data becomes stable with respect to active clock edge.
t
h(o)
: output hold time; output data stays stable with respect to active clock edge.
handbook, full pagewidth
1.5 V
clock input
tPD(o)
th(o)
data input
data output
data
transition
period
data
valid
th(i)
tsu(i)
MHB490
Fig.19 Memory clock timing.
handbook, full pagewidth
1.5 V
MCLKI
tPD
MCLKO
MHB491
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