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參數(shù)資料
| 型號(hào)： | SAA6712E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | GRAPHICS PROCESSOR, PBGA292 |
| 封裝： | 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292 |
| 文件頁數(shù)： | 44/64頁 |
| 文件大?。?/td> | 228K |
| 代理商： | SAA6712E |
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1999 Aug 25
44
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
8.3.3
G
AIN CORRECTION PULSE GENERATION
The GAINC signal is the delayed horizontal sync pulse (VHS). It is delayed with respect to half the dot clock. The first
edge of VHS is delayed by gainc_on_delay and the second edge by gainc_off_delay (see Fig.11). The polarity is
programmed by gainc_pol.
Fig.11 Gain adjustment and clamp pulse generation.
handbook, full pagewidth
MHB254
RGB data
GAINC
CLAMP
gainc_off_delay
gainc_on_delay
clamp_on
clamp_off
8.4
Video mode and synchronization signal
detection
TheSAA6712Ecanbeusedtobuildupauto-scansystems
using an external microcontroller. Therefore information
about the input resolution and timing are provided
(see Tables 5 and 6).Theflagspos_vsyncandpos_hsync
show the polarity of the synchronization signals at VVS
and VHS. If they are set to logic 1 they are active HIGH,
and their active edge is the falling edge. If these flags are
set to logic 0, they are active LOW.
For detecting Video Electronic Standard Association
(VESA) Power-down modes or a not connected input, the
presence of the synchronization signals will be detected:
it can be read via no_vsync, and no_hsync. These flags
areactiveHIGH.ThetimingoftheappliedRGBvideoinput
can be taken from v_lines reporting the number of lines of
a full frame. The horizontal timing can be calculated from
h_clocks. This register shows the length of a line in
numbersofreferenceclockperiods.Thereferenceclockis
equal to the panel clock PCLK in double pixel output mode
(48 bits in parallel), or it is half the panel clock PCLK in
single pixel output mode (24 bits in parallel).
If one of the above mentioned flags or counters changes
its value, it can be assumed that a new graphics mode has
been applied. In this case an interrupt at pin INT will be
generated. This port is active LOW.
The reset can be cleared by writing a logic 1 to intr_clear
at address 24.
For adjusting the RGB input interface to a new graphics
mode, the registers of the section RGB auto adjustment
are to be used. With this auto adjustment support it is
possible to measure the number of blanking pixels and
lines between the end of the synchronization pulses and
the active video. The horizontal and vertical back porch
blanking can be read out at black_pixels and black_lines.
The number of active pixels or lines will be reported from
non_black_pixels and non_black_lines. The first value
should be used for tuning the sample clocks PLL so that
this value corresponds to the number of pixels to be
sampled horizontally in this specific graphics mode.
To distinguish between blanking and active video
ref_colour is used. If the sample values of all three colour
components are below this value the pixel is treated as a
blanking pixel, otherwise it is treated as active video.
Additionally a reference pixel can be defined with ref_line
andref_pixel.TheR,G,andBcomponentsofthispixelare
sampled and available at ref_pixel_red, ref_pixel_green,
and ref_pixel_blue. They can be used for fine tuning the
external PLL in frequency and phase and for colour gain
adjustment.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6713AH | XGA analog input flat panel controller |
| SAA6713H | XGA dual input flat panel controller |
| SAA7110 | Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器) |
| SAA7111 | Video Input Processor VIP |
| SAA7120H | Digital video encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6713AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713AH/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6713H/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6721 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
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