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參數(shù)資料
| 型號： | SAA6712E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | GRAPHICS PROCESSOR, PBGA292 |
| 封裝： | 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292 |
| 文件頁數(shù)： | 49/64頁 |
| 文件大?。?/td> | 228K |
| 代理商： | SAA6712E |
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1999 Aug 25
49
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
8.8.2
S
YNC GENERATION
The start of the horizontal sync pulse is defined in
ovl_hs_start and the polarity in ovl_hs_pol. The sync pulse
length is defined in ovl_hs_length (see Fig.14). It is
possible to generate a Hsync pulse from one clock cycle
length up to longer than the horizontal overlay data.
The vertical sync pulse starts at ovl_vs_start and is always
one output frame line long.
8.8.3
D
ATA SAMPLING
Data sampling from the two ports OVA and OVB starts
from the beginning of the horizontal sync pulse, but the
number of clocks defined in ovl_hs_latency will decide
when reading data from the overlay port will start
(see Fig.14). The end of the sync pulse is not important.
Fig.14 Hsync generation and data sampling (Hsync latency = 2).
handbook, full pagewidth
MHB259
O0
O2
O4
O6
O8
O1
O3
O5
O7
O9
OVCLK
OVHS
OVA
OVB
ovl_hs_start
ovl_hs_length
ovl_hs_latency
ovl_h_length
OVACT
8.8.4
OVCLK
GATING
All of the above mentioned functions will only work during
internal processing of valid video data, and not during
internal blanking regions. This can give problems if the
overlay window is displayed at the left border of the picture
because the first pixels of a line will be processed due to
the internal pipeline structure. To overcome this, the
OVCLK can be gated to disable data processing by the
external OSD controller during internal blanking. Clock
gating is enabled by clk_gating_on.
8.9
Colour correction
The colour correction unit can be used to perform gamma
correction, change of brightness, and so on. This can be
achieved by means of a look-up table. Each colour
component value in an RGB pixel is used as a pointer into
this table. The value from the table will replace the
incoming colour.
Various tables exist for R, G, and B components.
Programming of a table must be performed using the
programming registers 47 to 49 (see the colour correction
section of the programming register Table 5). It must be
decided which component table should be written to
(red_prog, green_prog, blue_prog). In colour_index the
start address or the first incoming colour value for
programming must be written. Then subsequent writing to
colour_value fill the table. At this address the I
2
C-bus
address auto-increment stops, but the value programmed
into colour_index will be incremented. It is possible to write
to more than one table by enabling of programming
multiple colour components.
If the colour correction unit is switched to bypass mode
(when colour_correction_on is not asserted), the incoming
colours are used for further processing.
Writing to the colour correction table is possible during
data processing.
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PDF描述 |
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| SAA6713AH | XGA analog input flat panel controller |
| SAA6713H | XGA dual input flat panel controller |
| SAA7110 | Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準彩色譯碼器) |
| SAA7111 | Video Input Processor VIP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6713AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713AH/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6713H/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6721 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
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