- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385813 > SAA6712E (NXP SEMICONDUCTORS) ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% PDF資料下載
參數(shù)資料
| 型號： | SAA6712E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | GRAPHICS PROCESSOR, PBGA292 |
| 封裝： | 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292 |
| 文件頁數(shù)： | 43/64頁 |
| 文件大?。?/td> | 228K |
| 代理商： | SAA6712E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當(dāng)前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
1999 Aug 25
43
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
8.3
RGB input interface
8.3.1
RGB
DATA SAMPLING
Sampling is done on the rising edge or on both edges of
VCLK depending on the number of ADCs.
The sample window is defined by v_offset, h_offset,
v_length, and h_length.
The offset counters start counting from the second edge of
their reference signals, i.e. VVS for vertical offset and VHS
for horizontal offset. Figure 10 shows the horizontal offset.
The polarities of the sync signals are given with vs_pol and
hs_pol. The vertical sample offset is given in lines and the
horizontal offset is measured in pixels. The width of the
sample window is defined by the length counters.
The vertical width is measured in lines and the horizontal
width in pixels, but only even pixel numbers are allowed.
ThesampleclockfortheADCsisalwaysVCLK,butindual
ADC mode this clock is half the pixel clock. Because of
that, in dual ADC mode, both clock edges are used to
sample data by the ADCs.
Table 8
Clock relationships
In single ADC mode, with each VCLK clock, a pixel must
be sampled from port A. In dual ADC mode, at each VCLK
clock edge, a pixel must be sampled alternating from
port A or B. The flag adc_sample_seq selects from which
port data sampling starts after the active edge of the
horizontal synchronization pulse.
8.3.2
C
LAMP PULSE GENERATION
The clamp pulse is generated with respect to half the dot
clock. The counters values responsible for switching the
clamp pulse on or off are clamp_on and clamp_off. Both
start counting from the second edge of VHS. The polarity
of CLAMP is given with clamp_pol.
NUMBER OF
ADCs
VCLK
VCLK
SAMPLE EDGE
1
2
dot clock
1
2
dot clock
positive
both
Fig.10 RGB data sampling.
handbook, full pagewidth
MHB253
VHS
RGB data
h_offset
h_length
0
1
2
3
4
5
n
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6713AH | XGA analog input flat panel controller |
| SAA6713H | XGA dual input flat panel controller |
| SAA7110 | Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器) |
| SAA7111 | Video Input Processor VIP |
| SAA7120H | Digital video encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6713AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713AH/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6713H/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6721 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。