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參數(shù)資料
| 型號： | SAA6712E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | GRAPHICS PROCESSOR, PBGA292 |
| 封裝： | 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292 |
| 文件頁數(shù)： | 39/64頁 |
| 文件大?。?/td> | 228K |
| 代理商： | SAA6712E |
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1999 Aug 25
39
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
G
ENERAL CONFIGURATION
2
Line length controlling in active video region
Line length controlling disabled
Line length controlling enabled
Line length controlling in border region
Line length controlling disabled
Line length controlling enabled
Line length controlling in top blanking region
Line length controlling disabled
Line length controlling enabled
Output interface mode
Free running output interface timing (external SDRAM required)
Synchronous output interface timing (without external SDRAM)
Blanking mode
Normal operating mode
All data outputs are at LOW level (black colour)
Output interface enabling
Output interface disabled, no data processing
Output interface enabled, normal data processing
Data qualifier generation mode
Disable pulse generation at pin PDE during vertical syncs
Enable pulse generation at pin PDE during vertical syncs
Line synchronization
Normal mode
Do not use
203
W
D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
D4
logic 0
logic 1
D5
logic 0
logic 1
D6
logic 0
logic 1
D7
logic 0
logic 1
H
ORIZONTAL LINE LENGTH IN BLANKING REGION
Horizontal line length in blanking region
204 and 205
W
D10 to D0
H
ORIZONTAL LINE LENGTH IN BORDER REGION
Horizontal line length in border region
206 and 207
W
D10 to D0
H
ORIZONTAL LINE LENGTH IN ACTIVE VIDEO REGION
Horizontal line length in active video region
208 and 209
W
D10 to D0
V
ERTICAL FRAME END
Vertical frame length
210 and 211
W
D10 to D0
V
ERTICAL BORDER REGION START
Vertical start of border region
212 and 213
W
D10 to D0
V
ERTICAL ACTIVE VIDEO REGION START
Vertical start of active video region
214 and 215
W
D10 to D0
H
ORIZONTAL DELAY OF START OF VERTICAL SYNC
Horizontal start delay of vertical sync pulse at pin PVS
216 and 217
W
D10 to D0
NAME
SUBADDRESS
R/W
DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6713AH | XGA analog input flat panel controller |
| SAA6713H | XGA dual input flat panel controller |
| SAA7110 | Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器) |
| SAA7111 | Video Input Processor VIP |
| SAA7120H | Digital video encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6713AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713AH/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6713H/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6721 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
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