參數(shù)資料
型號(hào)： SAA6712E
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 數(shù)學(xué)處理器
英文描述： ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
中文描述： GRAPHICS PROCESSOR, PBGA292
封裝： 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁(yè)數(shù)： 29/64頁(yè)
文件大小： 228K
代理商： SAA6712E
1999 Aug 25
29
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
Clock distribution
C
LOCK MULTIPLEXING
Memory clock generation
Memory clock is taken from pin MCLKI
Memory clock is
1
2
PLL clock
Panel clock generation
Panel clock is equal system clock
Panel clock is generated by PLL clock and post-divider
PLL activation
PLL disabled
PLL enabled
PLL post-divider precision
1
2
clock precision disabled
1
2
clock precision enabled
PLL pre-divider precision
1
2
clock precision disabled
1
2
clock precision enabled
PLL post-divider activation
PLL post-divider disabled
PLL post-divider enabled
PLL pre-divider activation
PLL pre-divider disabled
PLL pre-divider enabled
External memory clock multiplexer
Enable memory clock
Use system clock as external memory clock
26
W
D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
D4
logic 0
logic 1
D5
logic 0
logic 1
D6
logic 0
logic 1
D7
logic 0
logic 1
P
RE
-
DIVIDER P
-
COUNTER
Pre-divider p-counter programming
27
W
D7 to D0
P
RE
-
DIVIDER N
-
COUNTER
Pre-divider n-counter programming
28
W
D7 to D0
P
RE
-
DIVIDER N
-
OFFSET
Pre-divider n-counter offset programming
29
W
D3 to D0
P
OST
-
DIVIDER P
-
COUNTER
Post-divider p-counter programming
30
W
D7 to D0
P
OST
-
DIVIDER N
-
COUNTER
Post-divider n-counter programming
31
W
D7 to D0
P
OST
-
DIVIDER N
-
OFFSET
Post-divider n-counter offset programming
32
W
D3 to D0
NAME
SUBADDRESS
R/W
DATA
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