- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385813 > SAA6712E (NXP SEMICONDUCTORS) ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% PDF資料下載
參數(shù)資料
| 型號(hào)： | SAA6712E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | GRAPHICS PROCESSOR, PBGA292 |
| 封裝： | 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292 |
| 文件頁數(shù)： | 45/64頁 |
| 文件大小： | 228K |
| 代理商： | SAA6712E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當(dāng)前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
1999 Aug 25
45
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
8.5
Memory interface
The SAA6712E features a 64 bits wide synchronous
DRAM interface. Both SDRAM and SGRAM devices can
be used. There is no difference in programming when
using SDRAM or SGRAM devices. The only thing that
must be considered is the amount of frame buffer memory,
which must be enough for the specific application.
If not the whole bandwidth of the 64 bits wide data bus is
needed, the data bus can be downsized to 48 or 32 bits.
This is done with the parameter data_width, see Table 9.
Table 9
Data bus width
Since the different timing parameters of various RAM
device types are different, all important timing values are
programmable and must be set-up according to the used
RAM types.
To reach a high effective bandwidth all access to the
external memory is organized in bursts. The larger the
number of subsequent read or write accesses the higher
the effective bandwidth. An effective bandwidth of 91%
can be reached by doing 64 words burst accesses.
The RAM devices support a maximum internal burst
length of 8 words only, so 8 of these bursts must be run
subsequently. This can be programmed by setting up the
RAM with SDRAM_burst_length_code taken from the
specification data of the SDRAM or SGRAM. The memory
interface must be programmed to 64 words bursts by
programming the RAM burst length SDRAM_burst_length
to 8, and the number of these bursts in burst_seq_length
to 8. The internal structure of the SAA6712E is optimized
for 64 words bursts.
8.5.1
M
EMORY INTERFACE LIMITATIONS
The timing parameters of the memory access can be
programmed to fulfil the timing restrictions of several
SDRAM or SGRAM devices. But there are some
limitations, as shown in Table 10.
data_width[1 and 0]
PROGRAMMED BUS WIDTH
(BITS)
0
1
2
32
48
64
Table 10
Memory interface limitations
8.5.2
I
NITIALIZATION OF EXTERNAL MEMORY
All SGRAM and SDRAM devices must be powered-up and initialized correctly. The SAA6712E memory interface is
implemented to fulfil the INTEL PC100 SDRAM specification.
Table 11 shows the required programming steps to initialize the memory correctly.
TIMING SYMBOL
PARAMETER
CONDITIONS
MINIMUM VALUE
(CLOCK PERIODS)
≥
2
CAS latency
Column Address Strobe (CAS)
latency
activate to command delay; Row
Address Strobe (RAS) to CAS delay
RAS to RAS bank activity delay
t
RCD
≥
2
t
RRD
t
RRD
≠
t
RCD
; proposal is
t
RRD
= t
RCD
+ 1
≥
3
t
RP
t
WR
t
RC
SDRAM_burst_length
RAS precharge time
write recovery time
RAS cycle time
≥
3
≥
1
≥
3
≥
2
must be supported by
SDRAM
must be an even number
internally defined; cannot be
changed
burst_seq_length
t
RSC
≥
2
=8
Register Set Cycle (RSC) mode time
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6713AH | XGA analog input flat panel controller |
| SAA6713H | XGA dual input flat panel controller |
| SAA7110 | Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器) |
| SAA7111 | Video Input Processor VIP |
| SAA7120H | Digital video encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6713AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713AH/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6713H/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6721 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。