參數(shù)資料
型號(hào)： SAA6712E
廠商： NXP SEMICONDUCTORS
元件分類： 數(shù)學(xué)處理器
英文描述： ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
中文描述： GRAPHICS PROCESSOR, PBGA292
封裝： 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁(yè)數(shù)： 13/64頁(yè)
文件大?。?/td> 228K
代理商： SAA6712E
1999 Aug 25
13
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
Notes
1.
Generally all inputs are 5 V tolerant TTL inputs. All outputs are CMOS, except the memory interface ports, which are
LVTTL compatible.
Connect to ground when not using the JTAG controller.
2.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
L18
P20
R20
U3
U5
U7
U14
U20
V20
W4
W15
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
SYMBOL
Pin
PORT
I/O
(1)
DESCRIPTION
7
FUNCTIONAL DESCRIPTION
7.1
Data path
Input video data is sampled either as RGB data in single
pixels from only one ADC or in double pixels in interleaved
format from two ADCs. The clock for sampling the data will
always be provided from external circuitry. The video
stream will be adapted from the input frame rate to the
output frame rate needed by the panel. Therefore a frame
buffer built of SDRAMs or SGRAMs is used. If the panel
supports the incoming frame rate from the RGB port, the
adaption can be done without external memory.
If zooming must be performed the upscaler behind the
memory interface will be enabled. For downscaling the
downscaler in front of the memory interface in the data
path will be used. A colour correction can be done via a
look-up table. The resulting video stream can now be
positioned elsewhere in the output data stream by the
panning unit. If an external OSD controller is embedded
into the system, its OSD window will be put into the video
stream by the OSD overlay port. Additionally the internal
OSD will be inserted in the next stage. The temporal
dithering allows true colour pictures to be displayed on
high colour panels. The output interface provides the
timing and control signals necessary for the connected
panel.
7.2
System clocks
7.2.1
I
NPUT INTERFACE CLOCK
(VCLK)
This clock is used for sampling the incoming RGB data
stream. In RGB mode this clock varies from
25 to 150 MHz in single ADC mode. If two ADCs are used
the RGB input clock is between 12.5 and 75 MHz.
The RGB clock can be generated by the external ADCs or
an external video PLL.
7.2.2
M
EMORY INTERFACE CLOCK
(MCLKI)
The memory clock is the synchronous clock for the
external frame buffer. Depending on the bandwidth
needed by the application, and the connected SDRAM or
SGRAM devices, the clock varies from 83 to 125 MHz.
It can be generated internally by the PLL from the system
clock (CLK), or by an external quartz oscillator.
If the internal PLL is used, the memory clock frequency
can be derived from the following formula:
N
Where N = pre-divider ratio and f_system = clock at
pin CLK.
f_memory
f_system
16
×
=
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