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參數(shù)資料
| 型號(hào)： | SAA6712E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 數(shù)學(xué)處理器 |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | GRAPHICS PROCESSOR, PBGA292 |
| 封裝： | 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292 |
| 文件頁(yè)數(shù)： | 30/64頁(yè) |
| 文件大?。?/td> | 228K |
| 代理商： | SAA6712E |
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1999 Aug 25
30
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
Input interface
G
ENERAL PROGRAMMING
Hsync polarity
Hsync is active LOW, line starts at rising edge of pin VHS
Hsync is active HIGH, line starts at falling edge of pin VHS
Vsync polarity
Vsync is active LOW, line starts at rising edge of pin VVS
Vsync is active HIGH, line starts at falling edge of pin VVS
Clamp pulse polarity
Pulse is active LOW
Pulse is active HIGH
Gain correction pulse polarity
Pulse is active LOW
Pulse is active HIGH
ADC sample sequence
ADC 0 is sampled first after Hsync (video input port A, B, C)
ADC 1 is sampled first after Hsync (video input port D, E, F)
Input interface activation
No data sampling
Data sampling enabled
33
W
D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
D4
logic 0
logic 1
D6
logic 0
logic 1
V
ERTICAL SAMPLE OFFSET
Vertical sample offset from Vsync
35 and 36
W
D10 to D0
H
ORIZONTAL SAMPLE OFFSET
Horizontal sample offset from Hsync
37 and 38
W
D11 to D0
V
ERTICAL SAMPLE LENGTH
Vertical sample window length
39 and 40
W
D10 to D0
H
ORIZONTAL SAMPLE LENGTH
Horizontal sample window length
41 and 42
W
D11 to D0
C
LAMP PULSE START
Start of clamp pulse after active edge of Hsync
43
W
D7 to D0
C
LAMP PULSE END
End of clamp pulse after active edge of Hsync
44
W
D7 to D0
G
AIN CORRECTION PULSE START DELAY
Delay of start of GAINC pulse from first edge of Hsync
45
W
D7 to D0
G
AIN CORRECTION PULSE END DELAY
Delay of end of pulse GAINC from second edge of Hsync
46
W
D7 to D0
NAME
SUBADDRESS
R/W
DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6713AH | XGA analog input flat panel controller |
| SAA6713H | XGA dual input flat panel controller |
| SAA7110 | Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器) |
| SAA7111 | Video Input Processor VIP |
| SAA7120H | Digital video encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6713AH | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713AH/V1 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713H | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6713H/V1 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6721 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
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