參數(shù)資料
型號(hào)： SAA6712E
廠商： NXP SEMICONDUCTORS
元件分類： 數(shù)學(xué)處理器
英文描述： ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
中文描述： GRAPHICS PROCESSOR, PBGA292
封裝： 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁(yè)數(shù)： 54/64頁(yè)
文件大小： 228K
代理商： SAA6712E
1999 Aug 25
54
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
8.12.3
T
IMING REFERENCE SIGNALS
The SAA6712E supports three timing reference signals to
drive the panels: PVS (vertical synchronization pulse),
PHS (horizontal synchronization pulse) and PDE (data
qualifier). The polarity of these signals is programmable.
To program high polarity the three programming registers
(vsync_pol, hsync_pol, de_pol) must be set to logic 1.
Sometimes panels require that no data qualifier signals
must be active during vertical synchronization.
The generation of PDE pulses during active PVS can be
switched off by de-asserting sync_de_inact.
The position and length of the horizontal synchronization
pulses in an output line must be programmed with
h_hs_start and h_hs_end. The vertical synchronization
pulse starts at line 0 and ends at v_vs_end. The horizontal
start offset in line 0 can be set-up with h_vs_start and the
horizontal end offset with h_vs_end.
The data qualifier PDE frames the display region that
should be visible on the panel horizontally. It will be
asserted at h_de_start and it will be de-asserted at
h_de_end. It frames both horizontal border and active
video region.
9
In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins are connected together and all
supply pins are connected together.
LIMITING VALUES
Note
1.
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k
resistor.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DDD
V
DD(PLL)
V
n
digital supply voltage
PLL supply voltage
voltage at digital inputs and outputs
voltage at digital output
voltage difference between V
SS(PLL)
and V
SS(D)
storage temperature
ambient temperature
operating bias ambient temperature
electrostatic handling voltage for all pins
0.5
0.5
+4.6
+4.6
+5.5
V
DDD
+ 0.5 V
100
+150
70
+70
+2
V
V
V
outputs in 3-state
0.5
outputs active
0.5
65
0
10
2
V
SS
T
stg
T
amb
T
amb(bias)
V
es
mV
°
C
°
C
°
C
kV
note 1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA6713AH 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller
SAA6713AH/V1 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller
SAA6713H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller
SAA6713H/V1 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller
SAA6721 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine
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