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參數(shù)資料
| 型號(hào)： | S568013MFA00E |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| 封裝： | ROHS COMPLIANT, LQFP-32 |
| 文件頁(yè)數(shù)： | 97/125頁(yè) |
| 文件大小： | 1702K |
| 代理商： | S568013MFA00E |
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Register Descriptions
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
73
01001 = Reserved for factory test—OCCS MSTR OSC clock
01011 = Reserved for factory test—ADC clock
01100 = Reserved for factory test—JTAG TCLK
01101 = Reserved for factory test—Continuous peripheral clock
01110 = Reserved for factory test—Continuous inverted peripheral clock
01111 = Reserved for factory test—Continuous high-speed peripheral clock
6.3.8
SIM GPIO Peripheral Select Register (SIM_GPS)
All of the peripheral pins on the 56F8013/56F8011 share their Input/Output (I/O) with GPIO ports. To
select peripheral or GPIO control, program corresponding bit in the GPIOx_PEREN register in GPIO
module. See the 56F801x Peripheral Reference Manual for detail. In some cases, there are two possible
peripherals as well as the GPIO functionality available for control of the I/O. In these cases, the SIM_GPS
register is used to determine which peripheral has control when the corresponding I/O pin is configured in
peripheral mode.
As shown in Figure 6-9, the GPIO Peripheral Enable Register (PEREN) has the final control over which
pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O when
PEREN = 1.
Figure 6-9 Overall Control of Pads Using SIM_GPS Control
Figure 6-10 GPIO Peripheral Select Register (SIM_GPS)
Base + $B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
TCR
PCR
0
CFG_
B7
CFG_
B6
CFG_
B5
CFG_
B4
CFG_
B3
CFG_
B2
CFG_
B1
CFG_
B0
CFG_A5
CFG_A4
Write
RESET
0
0000000
0000
GPIOB_PEREN Register
GPIO Controlled
I/O Pad Control
SIM_GPS Register
Quad Timer Controlled
SCI Controlled
0
1
0
1
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