
56F8013/56F8011 Data Sheet, Rev. 11
30
Freescale Semiconductor
4.2 Interrupt Vector Table
Table 4-2 provides the 56F8013/56F8011’s reset and interrupt priority structure, including on-chip
peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts
lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing
some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For
a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.5.11 for the reset value of the VBA.
By default, VBA = 0, and the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
Table 4-2 Interrupt Vector Table Contents1
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function
core
P:$00
Reserved for Reset Overlay2
core
P:$02
Reserved for COP Reset Overlay
core
2
3
P:$04
Illegal Instruction
core
3
P:$06
SW Interrupt 3
core
4
3
P:$08
HW Stack Overflow
core
5
3
P:$0A
Misaligned Long Word Access
core
6
1-3
P:$0C
EOnCE Step Counter
core
7
1-3
P:$0E
EOnCE Breakpoint Unit 0
core
8
1-3
P:$10
EOnCE Trace Buffer
core
9
1-3
P:$12
EOnCE Transmit Register Empty
core
10
1-3
P:$14
EOnCE Receive Register Full
core
11
2
P:$16
SW Interrupt 2
core
12
1
P:$18
SW Interrupt 1
core
13
0
P:$1A
SW Interrupt 0
14
Reserved
15
Reserved
PS
16
0-2
P:$20
Power Sense
OCCS
17
0-2
P:$22
PLL Lock, Loss of Clock Reference Interrupt
FM
18
0-2
P:$24
FM Access Error Interrupt
FM
19
0-2
P:$26
FM Command Complete
FM
20
0-2
P:$28
FM Command, data and address Buffers Empty
21
Reserved
GPIOD
22
0-2
P:$2C
GPIOD
GPIOC
23
0-2
P:$2E
GPIOC
GPIOB
24
0-2
P:$30
GPIOB