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參數(shù)資料
| 型號(hào)： | S568013MFA00E |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| 封裝： | ROHS COMPLIANT, LQFP-32 |
| 文件頁(yè)數(shù)： | 101/125頁(yè) |
| 文件大?。?/td> | 1702K |
| 代理商： | S568013MFA00E |
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Register Descriptions
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
77
6.3.9.4
Reserved—Bits 12–7
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.5
Timer Clock Enable (TMR)—Bit 6
0 = The clock is not provided to the Quad Timer module(the Quad Timer module is disabled)
1 = Clocks are enabled to the Quad Timer module
6.3.9.6
Reserved—Bit 5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.7
SCI Clock Enable (SCI)—Bit 4
0 = The clock is not provided to the SCI module (the SCI module is disabled)
1 = Clocks are enabled to the SCI module
6.3.9.8
Reserved—Bit 3
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.9
SPI Clock Enable (SPI)—Bit 2
0 = The clock is not provided to the SPI module (the SPI module is disabled)
1 = Clocks are enabled to the SPI module
6.3.9.10
Reserved—Bit 1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.11
PWM Clock Enable (PWM)—Bit 0
Each bit controls clocks to the indicated peripheral.
0 = The clock is not provided to the PWM module (the PWM module is disabled)
1 = Clocks are enabled to the PWM module
6.3.10
I/O Short Address Location Register (SIM_IOSAHI and
SIM_IOSALO)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in Figure 6-12.
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