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參數(shù)資料
| 型號(hào)： | S568013MFA00E |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| 封裝： | ROHS COMPLIANT, LQFP-32 |
| 文件頁(yè)數(shù)： | 19/125頁(yè) |
| 文件大?。?/td> | 1702K |
| 代理商： | S568013MFA00E |
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Equivalent Circuit for ADC Inputs
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
115
10.15 Equivalent Circuit for ADC Inputs
Figure 10-17 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed
at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to (VREFH-VREFL)/2, while the other charges to the analog input voltage. When the
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The switches switch
on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, VREF and the ADC clock frequency.
1.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
2.
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
3.
Equivalent resistance for the channel select mux; 100 ohms
4.
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pF
5.
Equivalent input impedance, when the the input is selected =
Figure 10-17 Equivalent Circuit for A/D Loading
10.16 Power Consumption
See Section 10.1 for a list of IDD requirements for the 56F8013/56F8011. This section provides additional
detail which can be used to optimize power consumption for a given application.
5. LSB = Least Significant Bit = 0.806mV
6. Pin groups are detailed following Table 10-1.
7. For device S56F8013MFA00E, input leakage current is ± 1
μA.
8. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the
ADC.
1
2
3
Analog Input
4
S1
S2
S3
C1
C2
S/H
C1 = C2 = 1pF
(VREFH- VREFL )/ 2
125
Ω ESD Resistor
8pF noise damping capacitor
1
(ADC Clock Rate) x 1.4 x 10-12
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