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參數(shù)資料
| 型號(hào)： | S568013MFA00E |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| 封裝： | ROHS COMPLIANT, LQFP-32 |
| 文件頁(yè)數(shù)： | 15/125頁(yè) |
| 文件大?。?/td> | 1702K |
| 代理商： | S568013MFA00E |
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Inter-Integrated Circuit Interface (I2C) Timing
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
111
10.12 Inter-Integrated Circuit Interface (I2C) Timing
Table 10-17 I2C Timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum
Maximum
Minimum
Maximum
SCL Clock Frequency
fSCL
0100
0400
kHz
Hold time (repeated )
START condition. After
this period, the first clock
pulse is generated.
tHD; STA
4.0
0.6
μs
LOW period of the SCL
clock
tLOW
4.7
1.25
μs
HIGH period of the SCL
clock
tHIGH
4.0
0.6
μs
Set-up time for a repeated
START condition
tSU; STA
4.7
0.6
μs
Data hold time for I2C bus
devices
tHD; DAT
01
1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH min of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
3.452
2. The maximum tHD; DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
01
0.92
μs
Data set-up time
tSU; DAT
250
1003
3. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT > = 250ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU; DAT = 1000 + 250 = 1250ns (according to the Standard mode I
2C bus specification) before the SCL line is
released.
ns
Rise time of both SDA and
SCL signals
tr
1000
2 +0.1Cb
4
4. Cb = total capacitance of the one bus line in pF.
300
ns
Fall time of both SDA and
SCL signals
tf
300
2 +0.1Cb
4
300
ns
Set-up time for STOP
condition
tSU; STO
4.0
0.6
μs
Bus free time between
STOP and START
condition
tBUF
4.7
1.3
μs
Pulse width of spikes that
must be suppressed by
the input filter
tSP
N/A
0.0
50
ns
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