參數(shù)資料
型號: S568013MFA00E
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 8 MHz, OTHER DSP, PQFP32
封裝: ROHS COMPLIANT, LQFP-32
文件頁數(shù): 48/125頁
文件大?。?/td> 1702K
代理商: S568013MFA00E
Pin Descriptions
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
29
3.5 Pin Descriptions
3.5.1
External Reference (GPIOB6 / RXD / SDA / CLKIN)
After reset, the internal relaxation oscillator is selected as the clock source for the chip. The user then has
the option of switching to an external clock reference if desired by enabling the PRECS bit in the OCCS
Oscillator Control register.
Figure 3-3 Connecting an External Clock Signal Using GPIOB6 / RXD / SDA / CLKIN
Part 4 Memory Map
4.1 Introduction
The 56F8013/56F8011 device is a 16-bit motor-control chip based on the 56800E core. It uses a
Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is
used in both spaces and Flash memory is used only in Program space.
This section provides memory maps for:
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8013
56F8011
Use Restrictions
Program Flash
(PFLASH)
8k x 16
6k x 16
Erase / Program via Flash interface unit and word writes to CDBW
Unified RAM (ram)
2k x 16
1k x 16
Usable by both the Program and Data memory spaces
56F801X
GPIO6/RXD/SDA/CLKIN
External
Clock
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