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| 型號(hào)： | S568013MFA00E |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| 封裝： | ROHS COMPLIANT, LQFP-32 |
| 文件頁(yè)數(shù)： | 105/125頁(yè) |
| 文件大?。?/td> | 1702K |
| 代理商： | S568013MFA00E |
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56F8013/56F8011 Data Sheet, Rev. 11
80
Freescale Semiconductor
The power modes provide additional means to disable clock domains, configure the voltage regulator, and
configure clock generation to manage power utilization, as shown in Table 6-3. Run, Wait, and Stop
modes provide means of enabling/disabling the peripheral and/or core clocking as a group. Stop disable
controls are provided for selected peripherals in the control register so that these peripheral clocks can
optionally continue to operate in Stop mode and generate interrupts which will return the part from Stop
to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is
possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction.
A 200kHz clock external clock can optionally be used in Standby mode to produce the required Standby
100kHz system bus rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully
disables the part and minimizes its power utilization but is only recoverable via reset.
When the PLL is not selected and the system bus is operating at around 100kHz, the large regulator can
be put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator.
Wait
Core and memory
clocks disabled
Peripheral clocks
enabled
Core executes WAIT instruction to enter this
mode.
Typically used for power-conscious applications.
Possible recoveries from Wait mode to Run
mode are:
1. Any interrupt
2. Executing a Debug mode entry command
during the 56800E core JTAG interface
2. Any reset (POR, external, software, COP)
Stop
Master clock generation in the OCCS
remains operational, but the SIM disables
the generation of system and peripheral
clocks.
Core executes STOP instruction to enter this
mode. Possible recoveries from Stop mode to
Run mode are:
1. Interrupt from Timer channels that have been
configured to operate in Stop mode (TCx_SD)
2. Interrupt for SCI configured to operate in Stop
mode (SCI_SD)
3. Low-voltage interrupt
4. Executing a Debug mode entry command
using the 56800E core JTAG interface
5. Any reset (POR, external, software, COP)
Standby
The OCCS generates the 2X system clock
at a reduced frequency (200kHz). The PLL
and high speed peripheral clocks are
disabled and the high-speed peripheral
option is not available. System and
peripheral clocks operate at 100kHz.
The user configures the OCCS and SIM to select
the relaxation oscillator clock source (PRECS),
shut down the PLL (PLLPD), put the relaxation
oscillator in Standby mode (ROSB), and put the
large regulator in Standby (LRSTDBY). The part
is fully operational, but operating at a minimum
frequency and power configuration. Recovery
requires reversing the sequence used to enter
this mode (allowing for PLL lock time).
Power-Down
Master clock generation in the OCCS is
completely shut down. All system and
peripheral clocks are disabled.
The user configures the OCCS and SIM to enter
Standby mode as shown in the previous
description, followed by powering down the
oscillator (ROPD). The only possible recoveries
from this mode are:
1. External Reset
2. Power-On Reset
Table 6-3 Clock Operation in Power-Down Modes (Continued)
Mode
Core Clocks
Peripheral Clocks
Description
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