參數(shù)資料
型號: S568013MFA00E
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 8 MHz, OTHER DSP, PQFP32
封裝: ROHS COMPLIANT, LQFP-32
文件頁數(shù): 86/125頁
文件大?。?/td> 1702K
代理商: S568013MFA00E
Resets
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
63
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
5.5.16.4
Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
0 = Normal operation (default)
1 = All interrupts disabled
5.5.16.5
Reserved—Bits 4–2
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.5.16.6
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6 Resets
5.6.1
General
5.6.2
Description of Reset Operation
5.6.2.1
Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in Figure 5-19.
Figure 5-19 Reset Interface
Table 5-4 Reset Summary
Reset
Priority
Source
Characteristics
Core Reset
RST
Core reset from the SIM
RES
CLK
VAB
PAB
RESET_VECTOR_ADR
READ_ADR
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