參數(shù)資料
型號: S568013MFA00E
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 8 MHz, OTHER DSP, PQFP32
封裝: ROHS COMPLIANT, LQFP-32
文件頁數(shù): 37/125頁
文件大?。?/td> 1702K
代理商: S568013MFA00E
56F8013/56F8011 Signal Pins
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
19
GPIOB7
(TXD)
(SCL2)
3
Input/
Output
Input/
Output
Input/
Output
Input with
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Transmit Data — SCI transmit data output or transmit / receive in
single wire operation.
Serial Clock — This pin serves as the I2C serial clock.
After reset, the default state is GPIOB7. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.
2. This signal is also brought out on the GPIOB0 pin.
RESET
(GPIOA7)
15
Input
Input/Open
Drain
Output
Input with
internal
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the chip is initialized and placed in the
reset state. A Schmitt trigger input is used for noise immunity. The
internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.
Port A GPIO — This GPIO pin can be individually programmed as
an input or open drain output pin. Note that RESET functionality is
disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.
After reset, the default state is RESET.
GPIOB4
(T0)
(CLKO)
19
Input/
Output
Input/
Output
Input with
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
T0 — Timer, Channel 0
Clock Output — This is a buffered clock signal. Using the
SIM_CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled (logic 0), CLK_MSTR
(system clock), IPBus clock, or oscillator output. See Section 6.3.7.
After reset, the default state is GPIOB4. The alternative peripheral
functionality is controlled via the SIM. See Section 6.3.8.
Return to Table 2-2
Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description
相關PDF資料
PDF描述
MC56F8023VLC 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP32
MC56F8033VLC 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP32
MC56F8347MPY60 16-BIT, 120 MHz, OTHER DSP, PQFP160
MC56F8355VFG60 4-BIT, 120 MHz, OTHER DSP, PQFP128
MC56F8355MFG60 4-BIT, 120 MHz, OTHER DSP, PQFP128
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