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參數(shù)資料
| 型號(hào)： | S568013MFA00E |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| 封裝： | ROHS COMPLIANT, LQFP-32 |
| 文件頁(yè)數(shù)： | 75/125頁(yè) |
| 文件大小： | 1702K |
| 代理商： | S568013MFA00E |
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Register Descriptions
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
53
5.5.2.8
PLL Loss of Reference or Change in Lock Status Interrupt Priority Level
(PLL IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.5.3
Interrupt Priority Register 2 (IPR2)
Figure 5-5 Interrupt Priority Register 2 (IPR2)
5.5.3.1
SCI Receiver Full Interrupt Priority Level (SCI_RCV IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.5.3.2
SCI Receiver Error Interrupt Priority Level (SCI_RERR IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.5.3.3
Reserved—Bits 11–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Base + $2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
SCI_RCV IPL
SCI_RERR
IPL
0
SCI_TIDL IPL
SCI_XMIT IPL SPI_XMIT IPL
SPI_RCV IPL
GPIOA IPL
Write
RESET
00000
0000000
0000
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