
S3FB42F MICROCONTROLLER
xv
List of Figures (Continued)
Figure
Title
Page
Number
19-1
Compatibility Hardware Handshaking Timing ..........................................................19-3
19-2
ECP Hardware Handshaking Timing (Forward)........................................................19-4
19-3
ECP Hardware Handshaking Timing (Reverse)........................................................19-4
20-1
A/D C Block Diagram...........................................................................................20-2
21-1
I2C-Bus Block Diagram ........................................................................................22-1
21-2
Multi-Master I2C-Bus Tx/Rx Data Register (IICDATA)..............................................22-5
21-3
Multi-Master I2C-Bus Address Register (IICADDR)..................................................22-6
22 -1
Top Block Diagram of Random Number Generator ..................................................22-2
22-2
Ring Oscillator Block ...........................................................................................22-4
23-1
USB Module Block Diagram .................................................................................23-2
23-2
Function Address Register ...................................................................................23-6
23-3
Power Management Register................................................................................23-7
23-4
Frame Number Low Register ................................................................................23-8
23-5
Frame Number High Register................................................................................23-8
23-6
Interrupt Pending Register ....................................................................................23-9
23-7
Interrupt Enable Register......................................................................................23-11
23-8
Endpoint Index Register .......................................................................................23-12
23-9
Endpoint Direction Register ..................................................................................23-12
23-10
EP0 CSR Register (EP0CSR)...............................................................................23-14
23-11
INCSR Register...................................................................................................23-16
23-12
OUT Control Status Register ................................................................................23-18
23-13
IN MAX Packet Register (INMAXP)........................................................................23-19
23-14
OUT MAX Packet Register ...................................................................................23-20
23-15
EP0 MAX Packet Register ...................................................................................23-21
23-16
Write Counter LO Regsiter ...................................................................................23-22
23-17
Write Counter HI Register.....................................................................................23-22
23-18
USB Enable Register...........................................................................................23-24
24-1
Flash memory structure .......................................................................................24-2
24-2
Flash Memory Control Register.............................................................................24-4