
S3FB42F
MAC2424
25-11
ARITHMETIC UNIT
The arithmetic unit performs several arithmetic operations on data operands. It is a 52-bit, single-cycle, non-pipelined
arithmetic unit. The arithmetic unit receives one operand from MAi, and another operand from P register. The source
and destination MA accumulator of arithmetic instruction is always the same.
The arithmetic unit can perform positive or negative accumulate, add, subtract, shift, and several other operations,
most of them in a single cycle. It uses two's complement arithmetics. Some flags (VMi, MV flag) are affected as a
result of the arithmetic unit output value. The flags represent the MA register status.
Rounding Provision
Rounding (by adding 800000h to the LSP of the MA register) can be performed by special instruction ("ERND"
instruction) in a single cycle: two's complement rounding. After rounding operation, the 24-bit least significant portion
of MA register are cleared and the 24-bit most significant portion of MA register are filled with the rounded value.
MA Shifting Capabilities
52-bit MA register can be shifted by 1-bit left or right. All of this shift operation is arithmetic shift operation.
Double Precision Multiplication Support
The arithmetic unit support for double precision multiplication by add or subtract instruction with an alignment option
of the P register. The P register can be aligned (shifting 24 bits to the right) before accumulating the partial
multiplication result.
Division Possibilities
Two specific instructions ("EDIVQ" and "ERESR" instruction) are used to implement a non-restoring conditional
add/subtract division algorithm. The division can be only signed and two operands (dividend and divisor) must be all
positive number. The dividend must be a 48-bit operand, located in MA register. : 4-bit extension nibble contains the
sign extension of the MA register in 24-bit operation mode. In 16-bit operation mode, the dividend must be a 32-bit
operand and 8-bit extension nibble in the MA register must be sign-extended. The divisor must be a 24-bit
operand(24-bit mode) or 16-bit operand with sign-extended to 24-bit, located in 24-bit most significant portion of the P
register. The 24-bit least significant portion of the P register must be zero.
To obtain a valid result , the value of the dividend must be strictly smaller than the value of divisor (reading operand as
fractional data). Else, the quotient could not be expressed in the correct format. (for example, quotient greater than 1
for fractional format). At the end of algorithm, the result is stored in the MA register. (the same which previously
contained the dividend) : the quotient in the 24-bit LSP, the significant bit remainder stored in the 24 MSP of the MA
register.
Typically 48/24 division can be executed with 24 elementary divide operations (32/24 division with 16 elementary
divide operations), preceded by 1 initialization instructions (This instruction is required to perform initial subtraction
operation.), and possibly followed by one restoring instruction which restores the true remainder (in case this last
one is useful for the next calculations). Note that lower precision can also be obtained by decreasing the number of
elementary division step applied.
The operation of elementary instructions for division is as follows.