
I2C-BUS INTERFACE
S3FB42F
21-4
MULTI-MASTER I2C-BUS CONTROL/STATUS REGISTER (IICSR)
The multi-master I2C-bus control/status register, ICCSR, four bits, ICCSR.3–ICCSR.0, are read-only status flags.
ICCSR register settings are used to control or monitor the following I2C-bus functions (see Figure):
— I2C-bus busy status flag
— Failed bus arbitration procedure status flag
— Slave address/address register match or general call received status flag
— Slave address 00000000B (general call) received status flag
— Last received bit status flag (not ACK = "1", ACK = "0")
Register
Address
R/W
Description
Reset Value
IICSR
0xB9
R/W
I2C-bus status register
00h
[0]
Last-received bit (LRB) status flag
IICSR[0] is automatically set to 1 whenever an ACK signal is
(read only)
not received during a last bit receive operation. When the last
receive bit is zero, an ACK signal is detected and the
last-received bit status flag is cleared.
[1]
General call status flag
IICSR[1] is automatically set to 1 whenever '00000000B',
(read only)
general call value is issued by the received slave address.
When the Start/stop condition was occurred, IICSR[1]
is cleared.
[2]
Master address call status flag
IICSR[2] is automatically set to 1 whenever the received slave
(read only)
address matches the address value in IICADDR register.
This bit is cleared after Start/stop condition is occurred.
[3]
Arbitration status flag
IICSR[3] is automatically set to 1 to indicate that a bus
(read only)
arbitration has been failed during I2C-bus interface.
The zero of IICSR[3] means okay status for the current
I2C-bus interface.
[4]
IIC operation status flag (read)
IICSR[4] is automatically set to 1 to indicate that the end of
shifting for byte or stop condition is occurred. This bit is cleared
when IIC operations are activated by writing IICCON.
IIC interrupt source enable (write)
In write operation for this bit, this bit value determines that
interrupt is enable or not to indicate the end of shifting for byte
or stop condition is occurred.
0: No interrupt, pending
1: IIC interrupt
[5]
IIC-bus busy status (read-only)
IICSR[5] indicates that IIC-bus is not busy and the '1' status
means IIC-bus is busy. This bit is set after start condition is
detected and cleared after stop condition is occurred.
[7:6]
SCL/SDA digital filter selection
Setting this bit enables digital filtering on all two signal inputs:
SCL and SDA.
00: Disable
01: 1 clock period
10: 2 clock period filtering
11: 3 clock period filtering