
xxii
S3FB42F MICROCONTROLLER
List of Instruction Descriptions (Continued)
Instruction
Full Instruction Name
Page
Mnemonic
Number
LD @idm
Load into Memory Indexed ...................................................................................8-64
LD
Load Register......................................................................................................8-65
LD
Load GPR:bankd, GPR:banks ..............................................................................8-66
LD
Load GPR, TBH/TBL............................................................................................8-67
LD
Load TBH/TBL, GPR............................................................................................8-68
LD SPR
Load SPR...........................................................................................................8-69
LD SPR0
Load SPR0 Immediate.........................................................................................8-70
LDC
Load Code ..........................................................................................................8-71
LJP
Conditional Jump.................................................................................................8-72
LLNK
Linked Subroutine Call Conditional ........................................................................8-73
LNK
Linked Subroutine Call (Pseudo Instruction) ..........................................................8-74
LNKS
Linked Subroutine Call .........................................................................................8-75
LRET
Return from Linked Subroutine Call .......................................................................8-76
NOP
No Operation.......................................................................................................8-77
OR
Bit-wise OR ........................................................................................................8-78
OR SR0
Bit-wise OR with SR0 ..........................................................................................8-79
POP
POP...................................................................................................................8-80
POP
POP to Register..................................................................................................8-81
PUSH
Push Register .....................................................................................................8-82
RET
Return from Subroutine ........................................................................................8-83
RL
Rotate Left ..........................................................................................................8-84
RLC
Rotate Left with Carry ..........................................................................................8-85
RR
Rotate Right........................................................................................................8-86
RRC
Rotate Right with Carry ........................................................................................8-87
SBC
Subtract with Carry ..............................................................................................8-88
SL
Shift Left .............................................................................................................8-89
SLA
Shift Left Arithmetic .............................................................................................8-90
SR
Shift Right...........................................................................................................8-91
SRA
Shift Right Arithmetic...........................................................................................8-92
STOP
Stop Operation (Pseudo Instruction) .....................................................................8-93
SUB
Subtract .............................................................................................................8-94
SWAP
Swap..................................................................................................................8-95
SYS
System ..............................................................................................................8-96
TM
Test Multiple Bits ................................................................................................8-97
XOR
Exclusive OR ......................................................................................................8-98