
xiv
S3FB42F MICROCONTROLLER
List of Figures (Continued)
Figure
Title
Page
Number
7-1
Coprocessor Interface Diagram .............................................................................7-1
7-2
Coprocessor Instruction Pipeline...........................................................................7-3
9-1
Simple Circuit Diagram ........................................................................................9-1
9-2
PLL Frequency Divider Data Register (PLLDATA)...................................................9-3
9-3
System Clock Circuit Diagram..............................................................................9-6
11-1
Port Data Register Structure.................................................................................11-1
12-1
Basic Timer Control Register (BTCON) ..................................................................12-1
12-2
Watchdog Timer Control Register (WDTCON) ........................................................12-2
12-3
Watchdog Timer Enable Register (WDTEN) ...........................................................12-2
12-4
Basic Timer & Watchdog Timer Functional Block Diagram ......................................12-3
13-1
Watch Timer Circuit Diagram................................................................................13-2
14-1
Timer A Control Register (TACON) ........................................................................14-1
14-2
Timer B Control Register (TBCON) ........................................................................14-2
14-3
Timer A, B Function Block Diagram ......................................................................14-3
15-1
Serial I/O Module Control Registers (SIOCON) .......................................................15-1
15-2
SIO Pre-scaler Register (SIOPS) ..........................................................................15-2
15-3
SIO Function Block Diagram ................................................................................15-2
15-4
Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4=0)...................15-3
15-5
Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4=1) ...................15-3
16-1
UART Block Diagram...........................................................................................16-1
16-2
UART Line Control Register (LCON) ......................................................................16-2
17-1
Simple System Configuration................................................................................17-1
17-2
I2S Basic Interface Format (Phillips)......................................................................17-2
17-3
LSI Interface Format (Sony)..................................................................................17-2
17-4
Timing for I2S Transmitter.....................................................................................17-4
17-5
Timing for I2S Receiver.........................................................................................17-4
18-1
Simple System Configuration................................................................................18-2
18-2
ECC Processor Block Diagram.............................................................................18-5