
EXCEPTIONS
S3FB42F
6-2
NMI EXCEPTION (EDGE SENSITIVE)
On the falling edge of a core input signal nNMI, the NMI exception is executed by loading the CALL instruction in IR
and 0h:0001h in PC. Therefore, when NMI exception is activated, the "CALL {0h:PM[00001h]}" instruction is
executed. When the NMI exception is executed, the ie bit (SR0[1]) becomes 0 and a core output signal nEXPACK
is generated to acknowledge the exception.
IRQ[0] EXCEPTION (LEVEL-SENSITIVE)
When a core input signal nIRQ[0] is low, SR0[6] (ie0) is high, and SR0[1] (ie) is high, IRQ[0] exception is generated,
and this will load the CALL instruction in IR (Instruction Register) and 0h:0002h in PC. Therefore, on an IRQ[0]
exception, the "CALL {0h:PM[00002h]}" instruction is executed. When the IRQ[0] exception is executed, SR0[1] (ie)
is set to 0 and a core output signal nEXPACK is generated to acknowledge the exception.
IRQ[1] EXCEPTION (LEVEL-SENSITIVE)
When a core input signal nIRQ[1] is low, SR0[7] (ie1) is high, and SR0[1] (ie) is high, IRQ[1] exception is generated,
and this will load the CALL instruction in IR (Instruction Register) and 0h:0003h in PC. Therefore, on an IRQ[1]
exception, the "CALL {0h:PM[00003h]}" instruction is executed. When the IRQ[1] exception is executed, SR0[1] (ie)
is set to 0 and a core output signal nEXPACK is generated to acknowledge the exception.
HARDWARE STACK FULL EXCEPTION
A Stack Full exception occurs when a stack operation is performed and as a result of the stack operation sptr[5]
(SF) is set to 1. If the stack exception enable bit, exe (SR0[5]), is 1, the Stack Full exception is served. One
exception to this rule is when nNMI causes a stack operation that sets sptr[5] (SF), since it has higher priority.
Handling a Stack Full exception may cause another Stack Full exception. In this case, the new exception is
ignored. On a Stack Full exception, the CALL instruction is loaded in IR (Instruction Register) and 0h:0004h in PC.
Therefore, when the Stack Full exception is activated, the "CALL {0h:PM[00004h]}" instruction is executed. When
the exception is executed, SR0[1] (ie) is set to 0, and a core output signal nEXPACK is generated to acknowledge
the exception.
BREAK EXCEPTION
Break exception is reserved only for an in-circuit debugger. When a core input signal, BKREQ, is high, the
CalmRISC core is halted or in the break mode, until BKREQ is deactivated. Another way to drive the CalmRISC core
into the break mode is by executing a break instruction, BREAK. When BREAK is fetched, it is decoded in the fetch
cycle (IF stage) and the CalmRISC core output signal nBKACK is generated in the second cycle (ID/MEM stage).
An in-circuit debugger generates BKREQ active by monitoring nBKACK to be active. BREAK instruction is exactly
the same as the NOP (no operation) instruction except that it does not increase the program counter and activates
nBKACK in the second cycle (or ID/MEM stage of the pipeline). There, once BREAK is encountered in the program
execution, it falls into a deadlock. BREAK instruction is reserved for in-circuit debuggers only, so it should not be
used in user programs.