
S3FB42F
MAC2424
25-9
Multiplier Accumulators
Each MAi (i=0,1) is organized as two regular 24-bit registers (MA0H, MA0L, MA1H, MA1L) and two 4-bit extension
nibble (MA0E, MA1E) in MSR1 register. The MAi accumulators can serve as the source operand, as well as the
destination operand of MA relevant instructions. Only one MA accumulator can be used as an operand at a time
according to the BKMA bit of the MSR1 register. If BKMA is set, MA1 register can be used, and if BKMA is reset,
MA0 register can be used. Data transfer between two MA accumulators is possible through “ELD MA1, MA0” and
“ELD MA0, MA1” instructions. These are the only cases when two MA accumulator is accessible independent on
BKMA bit and a full 52-bit MA accumulator is loaded.
The 24-bit most significant portion (MSP) of the MA register (MAiH) or the 24-bit least significant portion (LSP) of the
MA register (MAiL) can be written by the XB as an operand. When MAiH register is written, MAiL register is forced to
zero and MAiE extension nibble is sign-extended. When MAiL register is written, MAiH and MAiE are not changed.
In 16-bit operation mode, read or write operation on MAiL register is different from 24-bit operation mode. The
operation is same as PL register operation. When MAiL write operation, the 16-bit most significant portion of MAiL
register is written by the 16-bit least significant portion of XB bus, and 8-bit LSP of MAiL is forced to zero. On MAiL
read operation, the 16-bit most significant portion of MAiL register is read to the 16-bit least significant portion of XB
bus, and 8-bit MSP of XB is sign-extended. In case of 16-bit mode MAiH write operation, MAiE extension nibble is
not sign-extended.
Extension Nibbles
Extension nibbles MA0E and MA1E in MSR1 register offer protection against 48-bit overflows in 24-bit mode
operation. When the result of a 52-bit adder output crosses bit 47, it sets VMi flag of MSR1 register (MA register
Overflow flag). When the sign is lost beyond the MSB of the extension nibble, it sets MV flag of MSR1 (Memorized
Overflow flag) and latches the value.
In 16-bit mode, these extension nibbles are not used at all and 8-bit most significant portion of the MAiH register is
used as extension byte. If the result of a 52-bit adder output crosses bit 39, it sets VMi flag.
Overflow Protection in MA Registers
The multiplier accumulator saturation instruction (ESAT instruction) sets the destination MA register to the positive
negative maximum value, if selected MA register overflows (VMi bit of MSR1 register is set). In case of 24-bit mode,
saturation values are 7FFFFFFFFFFFh (positive overflow) or 800000000000h (negative overflow) for the MA register
and extension nibble is sign-extended. In case of 16-bit mode, saturation value is different. When positive overflow
occurs, the saturation value is 007FFFFFFF00h for MA register, and when negative overflow, the saturation value is
FF8000000000h.
Another saturation condition is when moving from MAiH register through XB bus. This saturation mode is enabled
when selected MA register overflows (VMi bit at MSR1 register is set), and overflow protection bit is enabled (OPM
bit at MSR1 register is set). In this case the saturation logic will substitute a limited data value having maximum
magnitude and the same sign as the source register. The MA register value itself is not changed at all. In case of 24-
bit mode, saturation values are 7FFFFFh (positive overflow) or 800000h (negative overflow) and in 16-bit mode,
saturation values are 007FFFh or FF8000h.
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Saturation by Instruction: "ESAT" Instruction & VMi
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Saturation by MA Read: Read MAiH & VMi & OPM