
MAC2424
S3FB42F
25-26
ARITHMETIC UNIT
Maximum-Minimum Possibilities
Two Cycle maximum/minimum operations are available with pointer latching and modification. One of the Ai
accumulator register holds the maximum value in a "EMAX" instruction, or the minimum value in a "EMIN"
instruction. In the first cycle, the one accumulator register is compared with the operand by "ECP" instruction, and
this instruction updates N flag value. In the second cycle, this value is copied to the above defined accumulator
register. The address pointer register which generates address (except RP3) can be post-modified according to the
specified mode in the instruction. When the new maximum or minimum number is found, the previous pointer value is
latched into the LSB 15-bit field of RP3 pointer register. For more details, refer to "EMAX" and "EMIN" instructions on
the instruction set.
The examples which searches block elements are as follows
Loop_Start:
ECP A, @RP0+S0
// Compare Two Values (S0 must be 0)
EMAX(EMIN) A, @RP0+S1
// Conditional Load (S1 must be search index)
JP Loop_Start
Conditional Instruction Execution
Some instructions can be performed according to the T flag value of MSR0 register. These instructions may operate
when the T flag is set, and do nothing if the T flag is cleared. The instructions which have suffix "T" are this type of
instructions. ("emod1" type instruction. The conditional instruction execution capabilities can reduce the use of
branch instructions which require several cycles.
Shifting Operations
A few options of shifting are available in the ARU and all of them are performed in a single cycle. All shift operations
performed in the ARU are arithmetic shift operations : i.e. right shift filling the MSBs with sign values and left shift
filling with LSBs with zeros. The source and destination operands are one of 24-bit Ai accumulator registers. The
shift instructions performed in the ARU are all conditional instructions. The shift amount is limited to 1 and 8, right or
left respectively. The shift with carry is also supported.
Multi-Precision Support
Various instructions which help multi-precision arithmetic operation, are provided in the MAC2424. The instructions
with suffix "C" indicates that the operation is performed on source operand and current carry flag value. By using this
instructions, double precision or more precision arithmetics can be accomplished. The following shows one example
of multi-precision arithmetic.
// 3-cycle Double Precision Addition (A:B + 2 memory operand)
EADD B, @RP0+S0
// Lower Part Addition
EINCC A
// Carry Propagation
EADD A, @RP0+S0
// Higher Part Addition