
S3FB42F
PARALLEL PORT INTERFACE
19-11
PARALLEL PORT INTERRUPT EVENT REGISTERS
The two parallel port interrupt event registers, PPINTCON and PPINTPND, control interrupt-related events for the
input signal originating from the host, as well as data reception, command reception, and invalid events. The parallel
port interrupt control register, PPINTCON, contains the interrupt enable bits for each interrupt event that is indicated
by the PPINTPND status bits. If the PPINTCON enable bit is "1", the corresponding event causes the S3FB42F CPU
to generate an interrupt request. Otherwise, no interrupt request is issued.
NOTE
To clear the corresponding pending bit to zero after a interrupt service routine, write the pending bit to zero.
The value of the pending bit is changed from one to zero automatically.
Register
Address
R/W
Description
Reset Value
PPINTCONL
0x66
R/W
Parallel port interrupt control low register
00h
PPINTPNDL
0x68
R/W
Parallel port interrupt pending low register
00h
[0]
nSLCTIN Low-to-High
The bit of PPINTPND is set when a Low-to-High transition on Nslctin
(P1284)
is detected. If the corresponding enable bit is set in the PPINTCON
register, an interrupt request is generated.
[1]
nSLCTIN High-to-Low
The bit of PPINTPND is set when a High-to-Low transition on nSLCTIN
is detected. If the corresponding enable bit is set in the PPINTCON
register, an interrupt request is generated.
[2]
nSTROBE Low-to-High
The bit of PPINTPND is set when a Low-to-High transition in the
(HostCLK)
nSTROBE is detected. If the corresponding enable bit is set in the
PPINTCON register, an interrupt request is generated.
[3]
nSTROBE High-to-Low
The bit of PPINTPND is set when a High-to-Low transition in the
nSTROBE is detected. If the corresponding enable bit is set in the
PPINTCON register, an interrupt request is generated.
[4]
nAUTOFD Low-to-High
The bit of PPINTPND is set when a Low-to-High transition in the
(HostACK)
nAUTOFD is detected. If the corresponding enable bit is set in the
PPINTCON register, an interrupt request is generated.
[5]
nAUTOFD High-to-Low
The bit of PPINTPND is set when a High-to-Low transition in the
nAUTOFD is detected. If the corresponding enable bit is set in the
PPINTCON register, an interrupt request is generated.
[6]
nINIT Low-to-High
The bit of PPINTPND is set when a Low-to-High transition in the nINIT
(nReverseRequest)
is detected. If the corresponding enable bit is set in the PPINTCON
register, an interrupt request is generated.
[7]
nINIT High-to-Low
The bit of PPINTPND is set when a High-to-Low transition in the nINIT
is detected. If the corresponding enable bit is set in the PPINTCON
register, an interrupt request is generated.