
MAC2424
S3FB42F
25-8
Multiplier
The Multiplier unit consists of a 24 by 24 to 48 bit parallel 2’s complement single-cycle, non-pipelined multiplier, 4
24-bit input registers (X0, X1, Y0, and Y1), a 48-bit output product register (P), and output shifter & saturation logic.
The multiplier performs signed by signed multiplication in 24-bit mode, and 4 quadrant multiplication in 16-bit mode.
Together with 52-bit adder in MAU, the MAC2424 can perform a single-cycle Multiply-Accumulate (MAC) operation.
The multiplier only operates when multiply instruction is executed. The P register is not updated and the multiplier is
not operated after a change in the input registers. This scheme reduces power consumption in multiplier.
In 16-bit operation mode, multiplier input registers, X and Y, are aligned (shifting 4 bits to the left) before
multiplication, and 32-bit output result is written in bit 39 to 8 of P register. The bit 47 to 40 of P register is sign-
extended, and lower 8-bit part are forced to 0.
PSH1 bit of MSR1 register indicates whether multiplier output is shifted 1 bit to the left or not. If PSH1 bit is set,
multiplier output is shifted 1 bit to the left. This operation can be used in the signed fractional multiplication. USM bit
of MSR1 register indicates whether multiplier input register is signed or unsigned in 16-bit operation mode. When
USM bit is set in 16-bit mode, X1 and Y1 register is interpreted as an unsigned operand. For example, if X1 and Y0
register is selected as multiplier input register, unsigned by signed multiplication is performed. If X1 and Y1 register
is selected, unsigned by unsigned multiplication is performed. Note that unsigned operation is only possible in the
16-bit mode.
The X or Y register is read or written via the XB bus, and Y register is written via YB when dual load instruction is
executed. The 24-bit most significant portion (MSP) of the P register (PH) or the 24-bit least significant portion (LSP)
of the P register (PL) can be written by the XB as an operand. When MSP of the P register is written, LSP of the P
register is forced to zero. When LSP of the P register is written, MSP of the P register is not changed. In 16-bit
operation mode, read or write operation on PL register is different from 24-bit operation mode. When PL write
operation, the 16-bit most significant portion of PL register is written by the 16-bit least significant portion of XB bus,
and 8-bit LSP of PL is forced to zero. On PL read operation, the 16-bit most significant portion of PL register is read
to the 16-bit least significant portion of XB bus, and 8-bit MSP of XB is sign-extended. The other registers performs
the same operation as 24-bit mode.
Overflow Protection in Multiplier
The only case the multiplier overflow occurs is when multiplying 800000h by 800000h in fractional 24-bit mode, and
8000h by 8000h in signed/signed fractional 16-bit mode. (These cases mean –1*-1) : the result should be normally 1,
which overflows fractional format. Thus, in this particular case, a multiplier saturation block forces the multiplier result
to 7FFFFFFFFFFFh (24-bit mode) or 007FFFFFFF00h (16-bit mode) after internal 1-bit shift to the left and write this
value to the product register P.
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Saturation Condition at 24-bit mode: ~Prod[47] & Prod[46] & PSH1
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Saturation Condition at 16-bit mode: ~Prod[39] & Prod[38] & PSH1 & SX & SY