
S3FB42F
USB
23-3
FUNCTION DESCRIPTION
Transceivers (XCVR)
The transceiver consists of a differential receiver, two single ended receivers and two drivers. That is capable of
transmitting and receiving data at 12 Mbit/sec and 1.5 Mbit/sec meeting the USB requirements.
Serial Interface Engine (SIE)
The Serial Interface Engine implements the protocol layer of the USB. It does the clock recovery, error checking,
data conversion between serial and parallel data, do the handshake on the USB bus if the packet was directed to it,
bus timeout if response from the host is late, and all other USB protocol related functions.
It consists of Phase Locked Loop (PLL) for clock recovery from the incoming data, CRC checker and generator, bit
stuff and bit removal logic, NRZI encoder/decoder, shift register for serial/parallel conversion, PID decoder, data
toggler and sync detect logic.
SIE Interface Unit (SIU)
The SIE Interface Unit interfaces with SIE to get the parallel data and pass on to the FIU. Other important function of
the SIU is to compare the device and endpoint address in the token packet with the valid device and endpoint
addresses from the embedded function, and generate a address valid signal to the SIE so it can complete the
handshake to FIU so they can get started waiting for the data phase.
Function Interface Unit (FIU)
Function Interface Unit consists of Endpoint0 and three additional endpoints for the embedded function. The
Endpoint0 logic consists of 16 byte bi-directional FIFO and all the control logic necessary to interface with the SIU
on one side and with the MCU interface logic on the other side. The control logic keeps track of data toggle bit in a
multiple packet transaction and resend of the data when the request is retried by the host. It handles the setting and
clearing of the endpoint stall bit. The OUT/SETUP data from the FIFO is read by the MCU interface and data for the
IN is loaded into the FIFO by MCU interface.
The three additional endpoints are programmable as In or Out endpoint, and they can be interrupt, bulk or
isochronous types. Each endpoint consists of 32, and 64 byte bi-directional FIFOs used in one direction only with
direction programmed via a control bit in their respective CSR register. The data transfers between the MCU and the
FIFOs are controlled by setting/clearing bits in the CSR. Interrupt may be generated on occurrence of some
significant events and this interrupt can be disabled by the firmware.
MCU Interface Unit (MIU)
This block of logic will allow the MCU to interface to the FIU units. This block will handle the MCU timing, address
decoding and data multiplexing.