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參數(shù)資料
| 型號(hào)： | S3FB42F-TX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 30 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, TQFP-100 |
| 文件頁(yè)數(shù)： | 229/432頁(yè) |
| 文件大小： | 1172K |
| 代理商： | S3FB42F-TX |
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S3FB42F
MAC2424
25-17
MA1E/MA0E
– Bit 15–12/Bit 11–8
These four bit nibbles are used as guard bits for MA registers in 24-bit mode operation. These bits are updated when
MA register write operation is occurred. In 16-bit mode operation these bits are not affected during MA write
operation. These bits are also written during MSR1 register write operation.
BKMA
– Bit 6
This bit defines current bank of MA register. Only one MA register of two MA registers is accessible at a time except
"ELD MA1, MA0" or "ELD MA0, MA1" instruction. The BKMA bit is only affected when MSR1 register write operation
or "ER/ES BKMA" instruction is used. When this bit is set, current bank of MA register is MA1 register, and when
this bit is clear, current bank of MA register is MA0 register. The BKMA bit is cleared by a processor reset.
PSH1
– Bit 5
This bit defines multiplier output shift operation. When this bit is set, multiplier output result is 1-bit shifted left. This
property can be used for fractional format operand multiplication. When this bit is clear, no shift is executed on the
multiplier output. The PSH1 bit can be modified by writing to MSR1 register or "ER/ES PSH1" instruction. The PSH1
bit is cleared by a processor reset.
USM
– Bit 4
The USM bit indicates that the X1 or Y1 register is signed or unsigned as a multiplicand. It is only used for product
calculation in 16-bit mode operation. In 24-bit mode operation, this bit has no effect. When set, selected multiplicand
is interpreted as a unsigned number if X1 or Y1 register is selected. The other registers (X0, Y0) are always signed
number. The USM bit can be modified by writing to MSR1 register or "ER/ES USM" instruction. The USM bit is
cleared by a processor reset.
OPM
– Bit 3
The OPM bit indicates that saturation arithmetic is provided or not when moving from the higher portion of one of the
MA registers through the XB bus. When the OPM bit is set(Overflow Protection is enabled), the saturation logic will
substitute a limited data value having maximum magnitude and the same sign as the source MA register. If the OPM
bit is clear, no saturation is performed. This bit has not effect on a "ESAT" instruction, which always saturates the
MA register value. The OPM bit is modified by writing the MSR1 register or "ER/ES OPM" instruction. The OPM bit
is cleared by a processor reset.
MV
– Bit 2
The MV bit is a memorized 52-bit overflow (in 24-bit mode) or 48-bit overflow (in 16-bit mode). This bit indicates that
the guard bits of MA register is overflowed during previous arithmetic operations. This bit is set when overflow on
guard bits is occurred and is not cleared when this overflow is cleared. It is only cleared when "ER MV" instruction or
MSR1 register write instruction is executed.
VM1/VM0
– Bit 1–0
These bits indicates arithmetic overflow on MA1 register and MA0 register respectively. One of these bits is set if an
arithmetic overflow (48-bit overflow when 24-bit operation mode or 40-bit overflow when 16-bit operation) occurs after
an arithmetic operation, and cleared otherwise. It represents that the result of an operation cannot be represented in
48 bits (in 24-bit mode) or 40 bits (in 16-bit mode). i.e. these bits are set when 5-bit value of MA[51:47] register is not
all the same in 24-bit mode or 9-bit value of MA[47:39] register is not all the same in 16-bit mode. These bits are
modified by writing the MSR1 register and one of these bits is written when "ER/ES VM" instruction or all arithmetic
instruction according to the current bank of MA register (BKMA bit).
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