
S3FB42F
8-BIT ANALOG-TO DIGITAL CONVERTER
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8-BIT ANALOG-TO-DIGITAL CONVERTER
OVERVIEW
The S3FB42F has six 8-bit resolution A/D converter input (ADC0 to ADC5). The 8-bit A/D converter (ADC) module
uses successive approximation logic to convert analog levels entering at one of the six input channels to equivalent
8-bit digital values (ADDATAH, ADDATAL). The analog input level must lie between the AVREF and AVSS values. The
A/D converter has the following components:
Analog comparator with successive approximation logic
D/A converter logic (resistor string type)
ADC control register (ADCON)
Six multiplexed analog data input pins (ADC0-ADC5)
8-bit A/D conversion data output register (ADDATAH, ADDATAL)
6-bit digital input port
AVREF and AVSS pins
FUNCTION DESCRIPTION
To initiate an analog-to-digital conversion procedure, you write the channel selection data in the A/D converter control
register ADCON to select one of the six analog input pins (ADCn, n = 0-5) and set the conversion start or enable bit,
ADCON.0. The conversion result data load to ADDATA register.
During a normal conversion, A/D C logic initially sets the successive approximation register to 80H
(the approximate half-way point of an 8-bit register). This register is then updated automatically during each
conversion step. The successive approximation block performs 8-bit conversions for one input channel at a time.
You can dynamically select different channels by manipulating the channel selection bit value (ADCON.6-4) in the
ADCON register. To start the A/D conversion, you should set a the enable bit, ADCON.0. When a conversion is
completed, ADCON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the
ADDATA register where it can be read. The A/D converter then enters an idle state. Remember to read the contents
of ADDATA before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion
result.
NOTE
Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the
analog level at the ADC0-ADC5 input pins during a conversion procedure be kept to an absolute minimum.
Any change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or
IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP or
IDLE mode after A/D C operation is finished.