
MAC2424
S3FB42F
25-18
RAM POINTER UNIT
The RAM Pointer Unit (RPU) performs all address storage and effective address calculations necessary to address
data operands in data memories. In addition, it supports latching of the modified register in maximum/minimum
operations and bit reverse address generation. This unit operates in parallel with other resources to minimize address
generation overhead. The RPU performs two types of arithmetics : linear or modulo. The RPU contains four 16-bit
indirect address pointer registers (RP0 ~ RP3, also referred to RPi) for indirect addressing, two 16-bit direct address
pointer registers (RPD0 ~ RPD1, also referred to RPDi) for short direct form addressing, four 16-bit indirect index
registers (SD0 ~ SD3, also referred to SDi) and its extensions (SD0E and SD3E), and two 16-bit modulo
configuration registers (MC0 and MC1, also referred to MCi) for modulo control. The MC0 register has effect on RP0
and RP1 pointer register, and the MC1 register has effect on RP2 and RP3 register.
All indirect pointer registers (RPi) and direct pointer registers (RPDi) can be used for both XA and YA for instructions
which use only one address register. In this case the X memory and Y memory can be viewed as a single
continuous data memory space. the bit 13 to bit 0 of RPi register and RPDi register defines address for X or Y
memory, and the bit 14 determines whether the address is for X memory or Y memory. The bit 15 of RPi indicates
whether the selected pointer is updated with modulo arithmetic. The RPU can access two data operand
simultaneously over XA and YA buses. In dual access case, RP0 is automatically selected as a X memory pointer
and RP3 is selected as a Y memory pointer regardless of bit 14 of RP0 and RP3.
All registers in the RPU may be read or written to by the XB as 16-bit data. The detailed block diagram of the RAM
Pointer Unit is shown in Figure 25-8.
ADDRESS MODIFICATION
The RPU can generate up to two 14-bit addresses every instruction cycle which can be post-modified by two
modifiers: linear and modulo modifier. The address modifiers allow the creation of data structures in the data memory
for circular buffers, delay lines, FIFOs, etc. Address modification is performed using 15-bit two's complement linear
arithmetics.
Linear (Step) Modifier
During one instruction cycle, one or two of the pointer register, RPi, can be post incremented/decremented by a 2's
complement 4-bit step (from –8 to +7). If XSD bit of MSR0 register is set, these 4-bit step is extended to 8-bit (from –
128 to +127) by concatenating index register with extended index register (SD0E, SD3E) when selected pointer is
RP0 or RP3. The selection of linear modifier type (one out of four) is included in the relevant instructions. The four
step values are stores in each index register SDi. If the instruction requires a data memory read operation, S0 (bit 3
to bit 0) or S1 (bit 7 to bit 4) field of SDi register is selected as a index value. If the instruction requires a data
memory write operation, D0 (bit 11 to bit 8) or D1(bit 15 to bit 12) field of SDi register is selected as an index value.