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參數(shù)資料
| 型號(hào)： | S1C62920D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63 |
| 封裝： | DIE-63 |
| 文件頁(yè)數(shù)： | 60/78頁(yè) |
| 文件大小： | 874K |
| 代理商： | S1C62920D |
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S1C62920 TECHNICAL MANUAL
EPSON
55
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.12 Interrupt and HALT
<Interrupt types>
The S1C62920 provides the following interrupt settings, each of which is maskable.
External interrupt:
Input port interrupt
(1 system)
Internal interrupt:
Clock timer interrupt
(3 systems)
Serial interface interrupt
(1 system)
R/F converter interrupt
(1 system)
To authorize interrupt, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask
registers must be set to "1" (enable).
When an interrupt occurs the interrupt flag is automatically reset to "0" (DI), and interrupts after that are
inhibited.
Figure 4.12.1 shows the configuration of the interrupt circuit.
<HALT>
The S1C62920 has HALT function that considerably reduce the current consumption when it is not neces-
sary.
The CPU enters the HALT status when the HALT instruction is executed.
In the HALT status, the operation of the CPU is stopped. However, the oscillation circuit operates. Reacti-
vating the CPU from the HALT status is done by generating an interrupt request. When it does not reacti-
vate upon an interrupt request, the watchdog timer will cause it to restart from the initial reset status.
Fig. 4.12.1 Configuration of the interrupt circuit
IRF
EIRF
K03
KCP03
K02
KCP02
K01
KCP01
K00
KCP00
IK0
EIK0
IT2
EIT2
IT1
EIT1
IT0
EIT0
Interrupt
vector
generation
circuit
Program counter
(low-order 4 bits)
INT
(interrupt request)
Mask option
Interrupt factor flag
Interrupt mask register
Input comparison register
Interrupt flag
ISIF
EISIF
VSS
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