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參數(shù)資料
| 型號： | S1C62920D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63 |
| 封裝： | DIE-63 |
| 文件頁數(shù)： | 32/78頁 |
| 文件大小： | 874K |
| 代理商： | S1C62920D |
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30
EPSON
S1C62920 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
(2) Segment allocation
The LCD driver has a segment decoder built-in, and the data bit (D0–D3) of the optional address in the
display memory area (60H–7FH) can be allocated to the optional segment. This makes design easy by
increasing the degree of freedom with which the liquid crystal panel can be designed.
The allocated segment displays when the bit for the display memory is set to "1", and goes out when bit
is set to "0".
Figure 4.7.5.4 shows an example of the relationship between the LCD segments (on the panel) and the
display memory for the case of 1/3 duty.
Fig. 4.7.5.4 Segment allocation
(3) Output specification
The segment terminals (SEG0–SEG21) can be selected with the mask option in each pair for either
segment signal output or DC output (VDD and VSS binary output).
When DC output is selected, the data corresponding to COM0 of each segment terminal is output.
When DC output is selected, either complementary output or Nch open drain output can be selected
for each terminal with the mask option.
Note: The terminal pairs are the combination of SEG2
× n and SEG2 × n + 1 (where n is an integer from 0
to 10).
aa'
f
f'
g'
g
ee'
d
d'
p'
p
c'
b'
b
c
SEG10
SEG11
SEG12
Common 0
Common 1
Common 2
7AH
7BH
7CH
7DH
Address
d
p
d'
p'
D3
c
g
c'
g'
D2
b
f
b'
f'
D1
a
e
a'
e'
D0
Data
Display memory allocation
SEG10
SEG11
SEG12
7A, D0
(a)
7A, D1
(b)
7D, D1
(f')
7B, D1
(f)
7B, D2
(g)
7A, D2
(c)
7B, D0
(e)
7A, D3
(d)
7B, D3
(p)
Pin address allocation
Common 0
Common 1
Common 2
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