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參數(shù)資料
| 型號： | S1C62920D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63 |
| 封裝： | DIE-63 |
| 文件頁數(shù)： | 35/78頁 |
| 文件大?。?/td> | 874K |
| 代理商： | S1C62920D |
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32
EPSON
S1C62920 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.8 Clock Timer
4.8.1 Configuration of clock timer
The S1C62920 has a built-in clock timer with OSC1 divided clock (256 Hz) as clock source. The clock timer
is configured of a 8-bit binary counter and the timer data (128–16 Hz and 8–1 Hz) can be read out by the
software.
Figure 4.8.1.1 is the block diagram for the clock timer.
Fig. 4.8.1.1 Block diagram for the clock timer
Ordinarily, this clock timer is used for all types of timing functions such as clocks.
4.8.2 Data reading and hold function
The 8 bits timer data are allocated to the address C9H and CAH.
C9H
D0: TM0 (128 Hz)
D1: TM1 (64 Hz)
D2: TM2 (32 Hz)
D3: TM3 (16 Hz)
CAH
D0: TM4 (8 Hz)
D1: TM5 (4 Hz)
D2: TM6 (2 Hz)
D3: TM7 (1 Hz)
Since the clock timer data has been allocated to two addresses, a carry is generated from the low-order data
within the count (TM0–TM3: 128–16 Hz) to the high-order data (TM4–TM7: 8–1 Hz). When this carry is
generated between the reading of the low-order data and the high-order data, a content combining the two
does not become the correct value (the low-order data is read as 0FH and the high-order data becomes the
value that is counted up 1 from that point).
The high-order data hold function in the S1C62920 is designed to operate to avoid this. This function
temporarily stops the counting up of the high-order data (by carry from the low-order data) at the point
where the low-order data has been read and consequently the time during which the high-order data is
held is the shorter of the two indicated here following.
1. Period until it reads the high-order data.
2. 0.48–1.5 msec (varies due to the timing of the reading)
Note: When the high-order data has previously been read, since the low-order data is not held, you should
be sure to first read from the low-order data.
4.8.3 Interrupt function
The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz and 2 Hz signals. Software can set
whether to mask any of these frequencies.
Figure 4.8.3.1 is the timing chart of the clock timer.
128 Hz–16 Hz
Data bus
32 Hz, 8 Hz, 2 Hz
256 Hz
Clock timer reset signal
Interrupt request
Interrupt
control
8 Hz–1 Hz
Clock timer
TMRST
TMRUN
fOSC1
OSC1
oscillation circuit
Clock timer RUN/STOP signal
Dividing
circuit
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