參數(shù)資料
型號(hào)： S1C62920D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63
封裝： DIE-63
文件頁(yè)數(shù)： 20/78頁(yè)
文件大?。?/td> 874K
代理商： S1C62920D
S1C62920 TECHNICAL MANUAL
EPSON
19
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
K00 interrupt is not used by the mask option setting, so that an interrupt does not occur at (2). At (3), K03
changes to "0"; the data of the terminal the interrupt used no longer matches the data of the input compari-
son register, so that interrupt occurs. As already explained, the condition for the interrupt to occur is the
change in the port data and contents of the input comparison register from matching to no matching.
Hence, in (4), when the no matching status changes to another no matching status, an interrupt does not
occur. Further, terminals which interrupt is not used do not affect the conditions for interrupt generation.
4.4.4 Control of input ports
Table 4.4.4.1 lists the input ports control bits and their addresses.
Table 4.4.4.1 Input port control bits
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
K00
KCP00
EIK0
R/W
IK0
K03
K02
K01
K00
KCP03
KCP02
KCP01
KCP00
0
EIK0
0
IK0
–
1
–
0
–
0
High
Enable
Yes
Low
Mask
No
K01
KCP01
0
K02
KCP02
0
R
0
K03
KCP03
0
91H
92H
F3H
FBH
*2
*5
*4
*7
Input port K00–K03
Input comparison register (K00–K03)
Unused
Interrupt mask register (K00–K03)
Unused
Interrupt factor flag (K00–K03)
R
R/W
R
*1 Initial value at the time of initial reset
*5 Constantly "0" when being read
*2 Not set in the circuit
*6 Refer to main manual
*3 Undefined
*7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
K00–K03: Input port data (91H)
Input data of the input port terminals can be read with these registers.
When "1" is read:
High level
When "0" is read:
Low level
Writing:
Invalid
The reading is "1" when the terminal voltage of the 4 bits of the input ports (K00–K03) goes high (VDD), and
"0" when the voltage goes low (VSS).
These bits are dedicated for reading, so writing cannot be done.
KCP00–KCP03: Input comparison registers (92H)
Interrupt condition for terminals K00–K03 can be set with this register.
When "1" is written:
Falling edge
When "0" is written:
Rising edge
Reading:
Valid
The interrupt conditions can be set for the rising or falling edge of input for each of the 4 bits (K00–K03),
through the input comparison registers (KCP00–KCP03).
An input comparison is done only with the ports in which the interrupt is used among K00-K03 by the
mask option setting.
At initial reset, these registers are set to "1".
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