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參數(shù)資料
| 型號： | S1C62920D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63 |
| 封裝： | DIE-63 |
| 文件頁數(shù)： | 19/78頁 |
| 文件大?。?/td> | 874K |
| 代理商： | S1C62920D |
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18
EPSON
S1C62920 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4.3 Interrupt function
All 4 bits of the input ports (K00–K03) provide the interrupt function. The conditions for issuing an inter-
rupt can be set by the software. Further, It is possible to set whether or not the interrupt will be used by the
mask option.
Figure 4.4.3.1 shows the configuration of K00–K03 interrupt circuit.
Fig. 4.4.3.1 Input interrupt circuit configuration
The input comparison register (KCP) are individually set for the input ports K00–K03, and can specify the
interrupt timing.
The input interrupt timing can select that the interrupt be generated at the rising edge of the input or that it
be generated at the falling edge according to the set value of the input comparison register (KCP00–
KCP03).
By setting the condition, the interrupt for K00–K03 (4 bits unit) are generated when an input port in which
an interrupt has been enabled by the mask option and the content of the input comparison register have
been changed from matching to no matching.
The interrupt mask register EIK0 enables the interrupt mask to be selected for K00–K03.
When the interrupt is generated, the interrupt factor flag (IK0) is set to "1".
Figure 4.4.3.2 shows an example of an interrupt for K00–K03.
Input interrupt mask option settings
Input comparison register
K03
K02
K01
K00
KCP03 KCP02 KCP01 KCP00
Use
Not use
1010
With the above setting, the interrupt of K00–K03 is generated under the following condition:
Input port
(1)
K03
K02
K01
K00
1
0
1
0
(Initial value)
↓
(2)
K03
K02
K01
K00
1
011
↓
(3)
K03
K02
K01
K00
0
011
→ Interrupt generation
↓
(4)
K03
K02
K01
K00
0
111
Because K00 interrupt is not used, an interrupt will be generated
when matching does not occur between the contents of the 3 bits
K01–K03 and the 3 bits input comparison register KCP01–KCP03.
Fig. 4.4.3.2 Example of interrupt of K00–K03
Data
bus
Input comparison
register (KCP00)
K00
Interrupt
request
Address
Interrupt factor
flag (IK0)
K01
K02
K03
Interrupt mask
register (EIK0)
Address
Mask option
VSS
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