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參數資料
| 型號： | S1C62920D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63 |
| 封裝： | DIE-63 |
| 文件頁數： | 39/78頁 |
| 文件大小： | 874K |
| 代理商： | S1C62920D |
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36
EPSON
S1C62920 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.9 Serial Interface (SIN, SOUT, SCLK, SRDY)
4.9.1 Configuration of serial interface
The S1C62920 has a synchronous clock type 8 bits serial interface built-in.
The configuration of the serial interface is shown in Figure 4.9.1.1.
The CPU, via the 8 bits shift register, can read the serial input data from the SIN terminal. Moreover, via
the same 8 bits shift register, it can convert parallel data to serial data and output it to the SOUT terminal.
The SCLK terminal outputs or inputs synchronous clock. When this serial interface is used in master mode
(internal clock mode: when the S1C62920 is to be the master for serial input/output), FOUT frequency that
is selected by the mask option is used for the synchronous clock, and the clock is output from the SCLK
terminal. When this serial interface is used in slave mode (external clock mode: when the S1C62920 is to be
the slave for serial input/output), input the synchronous clock to the SCLK terminal from a master device.
Also, when the serial interface is used in slave mode, SRDY signal which indicates whether or not the serial
interface is available to transmit or receive can be output to the SRDY terminal.
Fig. 4.9.1.1 Configuration of serial interface
The input/output ports of the serial interface are common used with the I/O ports P10–P13, and function
of these ports can be selected through the software.
P10–P13 terminals and serial input/output correspondence are as follows:
Master mode
Slave mode
P10 = SIN (I)
P11 = SOUT (O)
P12 = SCLK (O)
P12 = SCLK (I)
P13 = I/O port (I/O)
P13 = SRDY (O)
Note: At initial reset, P10–P13 are set to I/O ports.
When using the serial interface, switch the function (ESIF = "1") in the initial routine.
SD0–SD7
SIN
(P10)
SCLK
(P12)
SCS0
Output
latch
EISIF
Serial interface
interrupt control circuit
ISIF
SOUT
(P11)
SRDY
(P13)
SCTRG
Serial interface
activating circuit
Serial clock
counter
Serial clock
selector
Serial clock
generator
Shift register (8-bit)
FOUT
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