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參數(shù)資料
| 型號： | S1C62920D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63 |
| 封裝： | DIE-63 |
| 文件頁數(shù)： | 40/78頁 |
| 文件大?。?/td> | 874K |
| 代理商： | S1C62920D |
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S1C62920 TECHNICAL MANUAL
EPSON
37
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.9.2 Master mode and slave mode of serial interface
The serial interface of the S1C62920 has two types of operation mode: master mode and slave mode.
In the master mode, it uses an internal (FOUT) clock as synchronous clock of the built-in shift register,
generates this internal (FOUT) clock at the SCLK (P12) terminal and controls the external (slave side) serial
device.
In the slave mode, the synchronous clock output from the external (master side) serial device is input from
the SCLK (P12) terminal and uses it as the synchronous clock to the built-in shift register.
The master mode and slave mode are selected by writing data to SCS0 register. Writing "1" to the SCS0
register sets the serial interface into the master mode, and writing "0" sets into the slave mode.
When the serial interface is set in the master mode, the FOUT clock selected by the mask option is used as
the synchronous clock. It can be selected from among 4 types; OSC1, OSC1 /8, OSC1 /64 and OSC3.
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/output of the 8 bits serial data, is controlled as
follows:
At master mode, after output of 8 clocks from the SCLK (P12) terminal, clock output is automatically
suspended and SCLK (P12) terminal is fixed at high level.
At slave mode, after input of 8 clocks to the SCLK (P12) terminal, subsequent clock inputs are masked.
A sample basic serial input/output portion connection is shown in Figure 4.9.2.1.
Fig. 4.9.2.1 Sample basic connection of serial input/output section
4.9.3 Data input/output and interrupt function
The serial interface of S1C62920 can input/output data via the internal 8 bits shift register. The shift register
operates by synchronizing with either the synchronous clock output from SCLK (P12) terminal (master
mode), or the synchronous clock input to SCLK (P12) terminal (slave mode).
The serial interface generates interrupt on completion of the 8 bits serial data input/output. Detection of
serial data input/output is done by the counting of the synchronous clock SCLK; the clock completes
input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates inter-
rupt.
The serial data input/output procedure data is explained below:
(1) Serial data output procedure and interrupt
The S1C62920 serial interface is capable of output parallel data as serial data, in units of 8 bits.
By setting the parallel data to 4 bits registers SD0–SD3 (E9H) and SD4–SD7 (EAH) individually and
writing "1" to SCTRG bit (E8HD1), it synchronizes with the synchronous clock and serial data is
output at the SOUT (P11) terminal. The synchronous clock used here is as follows: in the master mode,
internal clock which is output to the SCLK (P12) terminal while in the slave mode, external clock which
is input from the SCLK (P12) terminal. The serial data output from the built-in shift register is shifted
with the falling edge of the SCLK signal.
S1C62920
SCLK
SOUT
SIN
Input terminal
External
serial device
CLK
SOUT
SIN
READY
S1C62920
SCLK
SOUT
SIN
SRDY
External
serial device
CLK
SOUT
SIN
Input terminal
(a) Master mode
(b) Slave mode
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