參數(shù)資料
型號(hào)： S1C62920D
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63
封裝： DIE-63
文件頁(yè)數(shù)： 43/78頁(yè)
文件大?。?/td> 874K
代理商： S1C62920D
40
EPSON
S1C62920 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
ESIF: Serial interface enable (E8HD0)
Sets P10–P13 to the input/output port for the serial interface.
When "1" is written:
Serial interface
When "0" is written:
I/O port
Reading:
Valid
The ESIF is the serial interface enable register and P10–P13 terminals become serial input/output terminals
(SIN, SOUT, SCLK, SRDY) when "1" is written, and they become I/O port terminals when "0" is written.
The P13 terminal functions as SRDY output terminal only in the slave mode, and in the master mode, it
functions as the I/O port terminal.
At initial reset, this register is set to "0".
SCS0: Clock mode selection (E8HD3)
Selects the clock mode for the serial interface.
When "1" is written:
Master mode (FOUT clock is used)
When "0" is written:
Slave mode (external clock is used)
Reading:
Valid
When "1" is written to SCS0, the serial interface enters in the master mode. When "0" is written, it enters in
the slave mode.
For the synchronous clock that is used in the master mode, the FOUT clock, witch is selected as a R02
special output specification and FOUT frequency by the mask option, is used. Therefore, the FOUT fre-
quency should be selected even if the R02 port is not used as a special output (FOUT output).
At initial reset, this register is set to "0".
SCTRG: Clock trigger/status (E8HD1)
This is a trigger to start input/output of synchronous clock (SCLK).
During writing operation
When "1" is written:
Trigger
When "0" is written:
No operation
When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK) input/
output is started.
As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed
prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/
reading on data registers SD0–SD7.)
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from performing
trigger input multiple times, as leads to malfunctioning.
Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the
trigger.
During reading operation
When "1" is read:
RUN status
When "0" is read:
STOP status
Writing:
Invalid
When read out this bit, it indicates the status of serial interface clock.
After "1" is written to SCTRG, this value is latched till serial interface clock stops (8 clock counts). There-
fore, if "1" is read, it indicates that the synchronous clock is in input/output operation.
When the synchronous clock input/output is completed, this latch is reset to "0".
At initial reset, this register is set to "0".
SD0–SD3, SD4–SD7: Serial interface data register (E9H, EAH)
These registers are used for writing and reading serial data.
During writing operation
When "1" is written:
High level
When "0" is written:
Low level
Writes serial data will be output to SOUT (P11) terminal. From the SOUT (P11) terminal, the data converted
to serial data as high (VDD) level bit for bits set at "1" and as low (VSS) level bit for bits set at "0".
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