參數(shù)資料
型號(hào)： S1C62920D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63
封裝： DIE-63
文件頁數(shù)： 55/78頁
文件大小： 874K
代理商： S1C62920D
S1C62920 TECHNICAL MANUAL
EPSON
51
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (R/F Converter)
RFRUN: R/F conversion RUN/STOP (D2HD1)
Starts R/F conversion and indicates the operating (RUN/STOP) status.
When "1" is written:
R/F conversion starts
When "0" is written:
R/F conversion stops
When "1" is read:
RUN status
When "0" is read:
STOP status
When "1" is written to RFRUN, R/F conversion starts. The register remains at "1" during R/F conversion
and is set to "0" when R/F conversion is terminated.
When "0" is written to RFRUN during R/F conversion, R/F conversion is paused.
This register is set to "0" at initial reset, when the time base counter or measurement counter overflows, or
when measurement is finished.
OVMC: Measurement counter overflow flag (D2HD2)
Indicates whether the measurement counter has overflown.
When "1" is read:
Overflow has occurred
When "0" is read:
Overflow has not occurred
When "1" is written:
Flag reset
When "0" is written:
No operation
If an overflow occurs while counting the oscillation of the sensor, OVMC is set to "1" and the interrupt
occurs at the same time.
This flag is reset by writing "1" or starting R/F conversion.
At initial reset, this flag is set to "0".
OVTBC: Time base counter overflow flag (D2HD3)
Indicates whether the time base counter has overflown.
When "1" is read:
Overflow has occurred
When "0" is read:
Overflow has not occurred
When "1" is written:
Flag reset
When "0" is written:
No operation
If an overflow occurs while counting the oscillation of the reference resistance, OVTBC is set to "1" and the
interrupt occurs at the same time.
This flag is reset by writing "1" or starting R/F conversion.
At initial reset, this flag is set to "0".
EIRF: Interrupt mask register (F1HD0)
Select whether to mask interrupt with the R/F converter.
When "1" is written:
Enable
When "0" is written:
Mask
Reading:
Valid
The R/F converter interrupt is permitted when "1" is written to EIRF. When "0" is written, interrupt is
masked.
At initial reset, this register is set to "0".
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