參數(shù)資料
型號(hào)： S1C62920D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63
封裝： DIE-63
文件頁(yè)數(shù)： 41/78頁(yè)
文件大?。?/td> 874K
代理商： S1C62920D
38
EPSON
S1C62920 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
When the output of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIF
(F8HD0) is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the inter-
rupt mask register EISIF (F0HD0). Note, however, that regardless of the setting of the interrupt mask
register, the interrupt factor flag is set to "1" after output of the 8 bits data.
(2) Serial data input procedure and interrupt
The S1C62920 serial interface is capable of inputting serial data as parallel data, in units of 8 bits.
The serial data is input from the SIN (P10) terminal, synchronizes with the synchronous clock, and is
sequentially read in the 8 bits shift register. As in the above item (1), the synchronous clock used here is
as follows: in the master mode, internal clock which is output to the SCLK (P12) terminal while in the
slave mode, external clock which is input from the SCLK (P12) terminal.
The serial data to the built-in shift register is read with the rising edge of the SCLK signal. Moreover,
the shift register is sequentially shifted as the data is fetched.
When the input of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIF is set to "1"
and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIF.
Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is
set to "1" after input of the 8 bits data.
The data input in the shift register can be read from data registers SD0–SD7 by software.
(3) Serial data input/output permutation
In the S1C62920, the input/output permutation of serial data is fixed at LSB first.
Fig. 4.9.3.1 Serial data input/output permutation
(4) SRDY signal
When the S1C62920 serial interface is used in the slave mode (external clock mode), SRDY is used to
indicate whether the internal serial interface is available to transmit or receive data for the master side
(external) serial device. SRDY signal is output from SRDY (P13) terminal.
SRDY signal becomes "0" (low) when the S1C62920 serial interface becomes available to transmit or
receive data; normally, it is at "1" (high).
SRDY signal changes from "1" to "0" immediately after "1" is written to SCTRG and returns from "0" to
"1" when "0" is input to SCLK (P12) terminal (i.e., when the serial input/output begins transmitting or
receiving data). Moreover, when data is read from or written to SD4–SD7, the SRDY signal returns to
"1".
(5) Timing chart
The S1C62920 serial interface timing chart is shown in Figure 4.9.3.2.
SIN
Address [EAH]
Address [E9H]
Output
latch
SOUT
SD3 SD2 SD1 SD0
SD7 SD6 SD5 SD4
(LSB first)
Fig. 4.9.3.2 Serial interface timing chart
SCTRG(W)
SCTRG(R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY(slave mode)
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