參數(shù)資料
型號(hào)： S1C62920D
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63
封裝： DIE-63
文件頁(yè)數(shù)： 29/78頁(yè)
文件大?。?/td> 874K
代理商： S1C62920D
S1C62920 TECHNICAL MANUAL
EPSON
27
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.7 LCD Driver (COM0–COM3, SEG0–SEG21)
4.7.1 Configuration of LCD driver
The S1C62920 has 4 common terminals (COM0–COM3) and 22 segment terminals (SEG0–SEG21), so that it
can drive an LCD with a maximum of 88 (22
× 4) segments.
The LCD drive voltage is generated by connecting VC2 to supply voltage VDD or VD1 generated from the
MCU internal circuit.
The driving method is 1/2 duty dynamic drive depending on the four types of potential, VSS, VC1, VC2 and
VC3. In addition to the 1/2 duty, 1/3 and 1/4 drive duty can be selected by the mask option. The frame
frequency is 32 Hz for 1/4 and 1/2 duty, and 42.7 Hz for 1/3 duty (fOSC1 = 32.768 kHz).
LCD display ON/OFF may be controlled by the software.
Note: "fOSC1" indicates the oscillation frequency of the OSC1 oscillation circuit.
4.7.2 LCD drive voltage
The LCD drive voltages VC1 and VC3 are generated internally by transforming VC2 into 1/2 and 3/2,
respectively. See Section 2.1.2, "Voltage <VC1, VC2 and VC3> for LCD driving" for the VC1 adjustment
method.
The LCD system power circuit that generates VC1 and VC3 is turned ON and OFF by the LCD power
control register LPWR.
By setting LPWR to "1", the LCD system power circuit generates VC1 and VC3. When LPWR is set to "0",
VC1 and VC3 become VC2 level. In this case, all outputs from the COM terminals and SEG terminals go to
VC2 level.
To display the LCD, the LCD drive power must be ON by previously setting LPWR to "1".
SEG output ports that are set for DC output by the mask option operate same as the output (R) port
regardless of the power ON/OFF control.
4.7.3 LCD display ON/OFF control
In the S1C62920, ON/OFF of the LCD display can be controlled by the LOFF register.
At initial reset, LOFF is set to "0", and the LCD display is set to the ON status.
The LCD power is OFF at initial reset, so the display is actually performed when the LCD power is turned
ON (LPWR = "1").
To set all of the LCD display OFF, write "1" to LOFF. With this, the SEG terminals output an OFF wave-
form.
4.7.4 Display memory area
The display memory is allocated in the data memory area, addresses 60H–7FH in page 1.
Since the display memory is write only, data modification by arithmetic instructions cannot be done.
Correspondence between segment outputs and bits within the display memory can be optionally set by the
mask option explained in the next section.
4.7.5 Mask option (drive duty selection and segment allocation)
(1) Drive duty selection
The LCD drive duty can be selected from among 3 types, 1/4, 1/3 and 1/2 duty by the mask option.
Table 4.7.5.1 shows the LCD drive duty setting.
Table 4.7.5.1 LCD drive duty setting
Duty
1/2
1/3
1/4
COM0, COM1
COM0–COM2
COM0–COM3
Frame frequency *
fOSC1/1,024 (32 Hz)
fOSC1/768 (42.7 Hz)
fOSC1/1,024 (32 Hz)
44 (22
× 2)
66 (22
× 3)
88 (22
× 4)
Terminals used
in common
Maximum number
of segments
* In case of fOSC1 = 32.768 kHz
Basically you should select the drive duty with the smallest drive segment number (for example, 1/3
duty for 60 segments and 1/2 duty for 40 segments) from among the drive duties permitting driving of
the segment number of the LCD panel.
Figures 4.7.5.1–4.7.5.3 show the dynamic drive waveform for 1/4 duty, 1/3 duty and 1/2 duty.
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