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參數(shù)資料
| 型號： | PSD833F2-15M |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 98/122頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PSD833F2-15M |
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Preliminary Information
PSD8XXF Family
73
9.6.1 Standard JTAG Signals (cont.)
The PSD8XXF supports JTAG In-System-Configuration (ISC) commands, but not
Boundary Scan. A definition of these JTAG-ISC commands and sequences are defined in
a supplemental document available from WSI. WSI’s PSDsoft software tool and FlashLink
JTAG programming cable implement these JTAG-ISC commands. This document is
needed only as a reference for designers who use a FlashLink to program their PSD8XXF.
9.6.2 JTAG Extensions
TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE”
command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They
are used to speed programming and erase functions by indicating status on PSD pins
instead of having to scan the status out serially using the standard JTAG channel. See
Application Note 54.
TERR will indicate if an error has occurred when erasing a sector or programming a byte in
Flash memory. This signal will go low (active) when an error condition occurs, and stay
low until an “ISC_CLEAR” command is executed or a chip reset pulse is received after an
“ISC-DISABLE” command.
TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will
be high when the PSD8XXF device is in read array mode (Flash memory and Boot Block
contents can be read). TSTAT will be low when Flash memory programming or erase
cycles are in progress, and also when data is being written to the Flash Boot Block.
TSTAT and TERR can be configured as open-drain type signals during an “ISC_ENABLE”
command. This facilitates a wired-OR connection of TSTAT signals from several PSD8XXF
devices and a wired-OR connection of TERR signals from those same devices. This is
useful when several PSD8XXF devices are “chained” together in a JTAG environment.
9.6.3 Security and Flash Memories Protection
When the security bit is set, the device cannot be read on a device programmer or through
the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed.
All other program/erase/verify commands are blocked. Full chip erase returns the part to a
non-secured blank state. The Security Bit can be set in PSDsoft Configuration.
All Flash Memory and Boot sectors can individually be sector protected against erasures.
The sector protect bits can be set in PSDsoft Configuration.
The
PSD8XXF
Functional
Blocks
(cont.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
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