- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄190254 > PSD833F2-15M 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 PDF資料下載
參數(shù)資料
| 型號： | PSD833F2-15M |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 73/122頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PSD833F2-15M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁當前第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁
PSD8XXF Family
Preliminary Information
50
The
PSD8XXF
Functional
Blocks
(cont.)
9.4 I/O Ports
There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight bits
except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing
multiple functions per port. The ports are configured using PSDsoft Configuration or by the
microcontroller writing to on-chip registers in the CSIOP address space.
The topics discussed in this section are:
General Port Architecture
Port Operating Modes
Port Configuration Registers
Port Data Registers
Individual Port Functionality.
9.4.1 General Port Architecture
The general architecture of the I/O Port is shown in Figure 22. Individual Port architectures
are shown in Figures 24 through 27. In general, once the purpose for a port pin has been
defined, that pin will no longer be available for other purposes. Exceptions will be noted.
As shown in Figure 22, the ports contain an output multiplexer whose selects are driven
by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft
Configuration. Inputs to the multiplexer include the following:
Output data from the Data Out Register
Latched address outputs
CPLD Micro
Cell output
External Chip Select from CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The PDB is connected to the Internal Data Bus for feedback and can be read by the
microcontroller. The Data Out and Micro
Cell outputs, Direction and Control Registers,
and port pin input are all connected to the PDB.
The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose
inputs come from the CPLD AND array enable product term and the Direction Register. If
the enable product term of any of the array outputs are not defined and that port pin is not
defined as a CPLD output in the PSDabel file, then the Direction Register has sole control
of the buffer that drives the port pin.
The contents of these registers can be altered by the microcontroller. The PDB feedback
path allows the microcontroller to check the contents of the registers.
Ports A, B, and C have embedded Input Micro
Cells (IMCs). The IMCs can be configured
as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by
the address strobe (AS/ALE) or a product term from the PLD AND array. The outputs from
the IMCs drive the PLD input bus and can be read by the microcontroller. Refer to the IMC
subsection of the PLD section.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD835G2V-B-90MI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-B-90U | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-B-90UI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-C-12B81I | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-C-12M | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。