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| 型號(hào)： | PSD833F2-15M |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁(yè)數(shù)： | 58/122頁(yè) |
| 文件大小： | 489K |
| 代理商： | PSD833F2-15M |
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PSD8XXF Family
Preliminary Information
36
The
PSD8XXF
Functional
Blocks
(cont.)
9.2.2.1 Output Micro
Cell
Eight of the Output Micro
Cells are connected to Ports A and B pins and are named as
McellAB0-7. The other eight Micro
Cells are connected to Ports B and C pins and are
named as McellBC0-7. If an McellAB output is not assigned to a specific pin in PSDabel,
the Micro
Cell Allocator will assign it to either Port A or B. The same is true for a McellBC
output on Port B or C. Table 16 shows the Micro
Cells and Port assignment.
Maximum
Native
Borrowed
Data Bit for
Output
Port
Product
Loading or
Micro
Cell
Assignment
Terms
Reading
McellAB0
Port A0, B0
3
6
D0
McellAB1
Port A1, B1
3
6
D1
McellAB2
Port A2, B2
3
6
D2
McellAB3
Port A3, B3
3
6
D3
McellAB4
Port A4, B4
3
6
D4
McellAB5
Port A5, B5
3
6
D5
McellAB6
Port A6, B6
3
6
D6
McellAB7
Port A7, B7
3
6
D7
McellBC0
Port B0, C0
4
5
D0
McellBC1
Port B1, C1
4
5
D1
McellBC2
Port B2, C2
4
5
D2
McellBC3
Port B3, C3
4
5
D3
McellBC4
Port B4, C4
4
6
D4
McellBC5
Port B5, C5
4
6
D5
McellBC6
Port B6, C6
4
6
D6
McellBC7
Port B7, C7
4
6
D7
Table 16. Output Micro
Cell Port and Data Bit Assignments
The Output Micro
Cell (OMC) architecture is shown in Figure 12. As shown in the figure,
there are native product terms available from the AND array, and borrowed product terms
available (if unused) from other OMCs. The polarity of the product term is controlled by the
XOR gate. The OMC can implement either sequential logic, using the flip-flop element, or
combinatorial logic. The multiplexer selects between the sequential or combinatorial logic
outputs. The multiplexer output can drive a Port pin and has a feedback path to the AND
array inputs.
The flip-flop in the OMC can be configured as a D, T, JK, or SR type in the PSDabel
program. The flip-flop’s clock, preset, and clear inputs may be driven from a product term
of the AND array. Alternatively, the external CLKIN signal can be used for the clock input
to the flip-flop. The flip-flop is clocked on the rising edge of the clock input. The preset and
clear are active-high inputs. Each clear input can use up to two product terms.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
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