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參數(shù)資料
| 型號(hào)： | PSD833F2-15M |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁(yè)數(shù)： | 96/122頁(yè) |
| 文件大小： | 489K |
| 代理商： | PSD833F2-15M |
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Preliminary Information
PSD8XXF Family
71
Port C Pin
JTAG Signals
Description
PC0
TMS
Mode Select
PC1
TCK
Clock
PC3
TSTAT
Status
PC4
TERR
Error Flag
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
Table 34. JTAG Port Signals
The
PSD8XXF
Functional
Blocks
(cont.)
9.6 Programming In-Circuit using the JTAG Interface
The JTAG interface on the PSD8XXF can be enabled on Port C (see Table 34). All
memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG interface. A blank part can be mounted on a printed circuit
board and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
*SR_cod and Periph Mode bits in the VM Register are always cleared to zero on power on or warm reset.
**
Port Configuration
Power On Reset
Warm Reset
Power Down Mode
MCU I/O
Input Mode
Unchanged
PLD Output
Valid after internal
Valid
Depend on inputs to
PSD configuration
PLD (address are
bits are loaded
blocked in PD mode)
Address Out
Tri-stated
Not defined
Data Port
Tri-stated
Peripheral I/O
Tri-stated
Table 33. Status During Power On Reset, Warm Reset and Power Down Mode
Register
Power On Reset
Warm Reset
Power Down Mode
PMMR0, 2
Cleared to “0”
Unchanged
Micro
Cells Flip
Cleared to “0” by
Depend on .re and
Flop status
internal power on
.pr equations
reset
VM Register*
Initialized based on
Unchanged
the selection in
PSDsoft
Configuration Menu.
All other registers
Cleared to “0”
Unchanged
9.5.3.4 Reset of Flash Erase and Programming Cycles (PSD8X4F Only)
An external reset on the RESET pin will also reset the internal Flash memory state
machine. When the Flash is in programming or erase mode, the RESET pin will terminate
the programming or erase operation and return the Flash back to read mode in tNLNH-A
(minimum 25 s) time.
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See WSI Application Note 54 for more details on JTAG In-System-Programming.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
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