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| 型號(hào)： | PSD833F2-15M |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁(yè)數(shù)： | 39/122頁(yè) |
| 文件大?。?/td> | 489K |
| 代理商： | PSD833F2-15M |
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Preliminary Information
PSD8XXF Family
The
PSD8XXF
Functional
Blocks
(cont.)
9.1.1.4 Power-Up Condition
The PSD8XXF internal logic is reset upon power-up to the read array mode. The FSi and
CSBOOTi select signals, along with the write strobe signal, must be in the false state
during power-up for maximum security of the data contents and to remove the possibility of
a byte being written on the first edge of a write strobe signal. Any write cycle initiation is
locked when VCC is below VLKO.
9.1.1.5 Read
Under typical conditions, the microcontroller may read the Flash, or Flash Boot
memories using read operations just as it would a ROM or RAM device. Alternately, the
microcontoller may use read operations to obtain status information about a program or
erase operation in progress. Lastly, the microcontroller may use instructions to read
special data from these memories. The following sections describe these read functions.
9.1.1.5.1 Read the Contents of Memory
Main Flash and Flash Boot memories are placed in the read array mode after power-up,
chip reset, or a Reset Flash instruction (see Table 9). The microcontroller can read the
memory contents of main Flash or Flash Boot by using read operations any time the read
operation is not part of an instruction sequence.
9.1.1.5.2 Read the Main Flash Memory Identifier
The main Flash memory identifier is read with an instruction composed of 4 operations:
3 specific write operations and a read operation (see Table 9). During the read operation,
address bits A6, A1, and A0 must be 0,0,1, respectively, and the appropriate sector select
signal (FSi) must be active. The PSD8XXF main Flash memory ID is E7h. (PSD833F2,
PSD834F2) and E4h (PSD813FX).
9.1.1.5.3 Read the Flash Memory Sector Protection Status
The Flash memory sector protection status is read with an instruction composed of 4
operations: 3 specific write operations and a read operation (see Table 9). During the read
operation, address bits A6, A1, and A0 must be 0,1,0, respectively, while the chip select
(FSi or CSBOOTi) designates the Flash sector whose protection has to be verified. The
read operation will produce 01h if the Flash sector is protected, or 00h if the sector is not
protected.
The sector protection status for all NVM blocks (main Flash or Boot Flash) can also be
read by the microcontroller accessing the Flash Protection and Flash Boot Protection
registers in PSD I/O space. See section 9.1.1.9.1 for register definitions.
9.1.1.5.4 Read the Erase/Program Status Bits
The PSD8XXF provides several status bits to be used by the microcontroller to confirm
the completion of an erase or programming instruction of Flash memory. These status bits
minimize the time that the microcontroller spends performing these tasks and are defined
in Table 10. The status bits can be read as many times as needed.
19
FSi/
CSBOOTi
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Data
Toggle
Error
Erase
Flash
VIH
Polling
Flag
XTime-
X
out
Table 10. Status Bits
NOTES: 1. X = Not guaranteed value, can be read either 1 or 0.
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FSi/CSBOOTi are active high.
For Flash memory, the microcontroller can perform a read operation to obtain these status
bits while an erase or program instruction is being executed by the embedded algorithm.
See section 9.1.1.7 for details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD835G2V-B-90MI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-B-90U | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-B-90UI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-C-12B81I | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-C-12M | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
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